`include "macros.v"
-`define BRAM_ADDR_WIDTH 8
+`define BRAM_ADDR_WIDTH 14
`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
`define BRAM_NAME icache_bram
`include "bram.inc"
`defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
reg ihorn_full;
+ initial ihorn_full = 0;
reg dhorn_full;
+ initial dhorn_full = 0;
reg command_valid;
+ initial command_valid = 0;
reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
+ initial preload_size = 0;
+
reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
wire [(`BRAM_DATA_WIDTH-1):0] ramread;
reg command_valid_read;
+ initial command_valid_read = 0;
+
+ reg launched;
+ initial launched = 0;
+
+ icache_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
always @(posedge clk) begin
- if (command_valid_read) begin
- command_valid <= 1;
- command <= ramread;
- end
+ write_flag <= 0;
if (!write_addr_r && write_addr_a) write_addr_a = 0;
if (!write_data_r && write_data_a) write_data_a = 0;
- if (send_done) begin
+ if (command_valid_read) begin
+ command_valid_read <= 0;
+ command_valid <= 1;
+
+ end else if (send_done) begin
`onwrite(write_done_r, write_done_a)
send_done <= 0;
end
write_addr_a = 1;
write_data_a = 1;
send_done <= 1;
- write_flag = 1;
- write_addr = write_addr_d;
- write_data = write_data_d;
+ write_flag <= 1;
+ write_addr <= write_addr_d;
+ write_data <= write_data_d;
- end else if (ihorn_full) begin
+ end else if (ihorn_full && launched) begin
`onwrite(ihorn_r, ihorn_a)
ihorn_full <= 0;
end
end else if (command_valid) begin
command_valid <= 0;
+ command = ramread;
case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
0: begin
ihorn_full <= 1;
endcase
end else if (cbd_pos < cbd_size) begin
- command_valid <= 1;
- current_instruction_read_from = cbd_base+cbd_pos;
- command <= ram[current_instruction_read_from];
+ current_instruction_read_from <= cbd_base+cbd_pos;
+ command_valid_read <= 1;
cbd_pos <= cbd_pos + 1;
end else begin
`onread(preload_r, preload_a)
if (preload_size == 0) begin
preload_size <= preload_d;
- end else begin
- write_flag = 1;
- write_data = preload_d;
- write_addr = preload_pos;
+ end else if (!launched) begin
+ write_flag <= 1;
+ write_data <= preload_d;
+ write_addr <= preload_pos;
if (preload_pos == 0) begin
temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
cbd_pos <= 0;
cbd_base <= temp_base;
cbd_size <= temp_size;
+ launched <= 1;
end
preload_pos <= preload_pos + 1;
end
end
end
end
-
- if (write_flag) begin
- write_flag = 0;
- ram[write_addr] <= write_data;
- end
end
endmodule