}\r
\r
ISR(SIG_UART1_DATA) {\r
- //if (write_empty()) return;\r
+\r
+ if (write_empty()) {\r
+ UCSR1B &= ~(1 << UDRIE1);\r
+ return;\r
+ }\r
+ /*\r
portd(1, 0);\r
_delay_ms(10);\r
portd(1, 1);\r
_delay_ms(10);\r
- UCSR1B &= ~(1 << UDRIE1);\r
+ */\r
+ char ret = write_buf[write_buf_head];\r
+ write_buf_head = inc(write_buf_head);\r
+ UDR1 = (int)ret;\r
+\r
sei();\r
}\r
\r
void send(char c) {\r
\r
+ while (write_full());\r
+\r
write_buf[write_buf_tail] = c;\r
write_buf_tail = inc(write_buf_tail);\r
\r
UCSR1B |= (1 << UDRIE1);\r
\r
- while(!(UCSR1A & (1 << UDRE1))); /* Wait for data Regiester to be empty */\r
- char ret = write_buf[write_buf_head];\r
- write_buf_head = inc(write_buf_head);\r
- UDR1 = (int)ret;\r
+ //while(!(UCSR1A & (1 << UDRE1))); /* Wait for data Regiester to be empty */\r
}\r
\r
\r
}\r
\r
#define TIMERVAL 100\r
+static volatile int sending = 0;\r
ISR(SIG_OVERFLOW0) { \r
PORTD = ~FISUA;\r
TCNT0 = TIMERVAL; // load the nearest-to-one-second value into the timer0\r
- TIMSK |= (1<<TOIE0); //enable the compare match1 interrupt and the timer/counter0 overflow interrupt\r
+ TIMSK |= (1<<TOIE0); // enable the compare match1 interrupt and the timer/counter0 overflow interrupt\r
+ if (sending) UDR1 = FISUA;\r
sei();\r
} \r
void init_timer() { \r
case 3:\r
init_timer();\r
break;\r
+ case 4:\r
+ sending = 1;\r
+ break;\r
+ case 5:\r
+ sending = 0;\r
+ break;\r
default: die();\r
}\r
}\r