if(pc == -1) throw new Error("pc modifying insn in delay slot");
int target = (pc&0xf0000000)|(jumpTarget << 2);
emitInstruction(-1,nextInsn,-1);
- if(optimizedMemcpy && (target == memcpy || target == memset)) {
- if(target == memcpy)
- p("memcpy(r4,r5,r6);");
- else if(target == memset)
- p("memset(r4,r5,r6);");
- p("r2 = r4;");
- branch(pc,pc+8);
- } else {
- p("r" + RA + "=" + constant(pc+8 /*skip this insn and delay slot*/) + ";");
- branch(pc, target);
- }
+ p("r" + RA + "=" + constant(pc+8 /*skip this insn and delay slot*/) + ";");
+ branch(pc, target);
unreachable = true;
break;
}
p( "r"+rt+" = r"+rs+" < "+signedImmediate+" ? 1 : 0;");
break;
case 11: // SLTIU
- p( "r"+rt+" = (r"+rs+"&0xffffffffL) < ("+unsignedImmediate+"&0xffffffffL) ? 1 : 0;");
+ p( "r"+rt+" = (r"+rs+"&0xffffffffL) < ("+signedImmediate+"&0xffffffffL) ? 1 : 0;");
break;
case 12: // ANDI
p( "r"+rt+" = r"+rs+" & "+unsignedImmediate+";");
memWrite("addr","tmp");
break;
}
- // FEATURE: Need to be atomic if threads
+ // Need to be atomic if threads
case 48: // LWC0/LL
memRead("r"+rs+"+"+signedImmediate,"r"+rt);
break;
case 49: // LWC1
memRead("r"+rs+"+"+signedImmediate,"f"+rt);
break;
- // FEATURE: Needs to be atomic if threads
+ // Needs to be atomic if threads
case 56: // SWC1/SC
memWrite("r"+rs+"+"+signedImmediate,"r"+rt);
p("r" + rt + "=1;");