import com.sun.async.test.VerilogModel;
import edu.berkeley.fleet.api.Instruction;
+import edu.berkeley.fleet.marina.MarinaPath;
/** The Marina object will eventually represent the Marina test chip.
* Right now, it doesn't do much of anything. It just helps me exercise
* my test infrastructure. */
public class Marina {
+ public static final int INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ONE = 5;
+ public static final int INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO = MarinaPath.SIGNAL_BIT_INDEX;
+
public static final String DATA_CHAIN = "marina.marina_data";
public static final String CONTROL_CHAIN = "marina.marina_control";
public static final String REPORT_CHAIN = "marina.marina_report";
public int getCount() {
return value & 0x3f;
}
+ public String toString() {
+ return "[ilc, count="+getCount()+", infinity="+getInfinity()+", done="+getDone()+"]";
+ }
}
private final Indenter indenter;
this.cc = cc;
this.model = model;
this.indenter = indenter;
- data = new ProperStopper("northFif@1.fillDrai@1.properSt@1",
+ data = new ProperStopper("north fifo",
+ "northFif@1.fillDrai@1.properSt@1",
CONTROL_CHAIN,
DATA_CHAIN,
REPORT_CHAIN,
cc, model, clockHack, indenter);
- instrIn = new InstructionStopper("southFif@1.tapPropS@1.properSt@1",
+ instrIn = new InstructionStopper("south fifo",
+ "southFif@1.tapPropS@1.properSt@1",
CONTROL_CHAIN,
DATA_CHAIN,
REPORT_CHAIN,
vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__clr_", 1);
vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__set_", 0);
vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__clr_", 1);
- vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__set_", 0);
- vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__clr_", 1);
+
+ vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__set_", 1);
+ vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__clr_", 0);
+
vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@0.net_50", 0); // A
vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@1.net_50", 0); // B
vm.setNodeState("outputDo@0.outM1Pre@0.litDandP@0.latch2in@0.hi2inLat@0.latchKee@0.out_B_", 0); // C
+ // possible C-flag inputs
+ vm.setNodeState("northFif@1.upDown8w@2.weakStag@22.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ONE+1)+"]", 0);
+ vm.setNodeState("northFif@1.upDown8w@2.weakStag@22.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO+1)+"]", 0);
+
// force the OLC to zero
- for(int i=1; i<=6; i++)
- vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.inLO["+i+"]", (i==1)?0:1);
+ if (!kesselsCounter)
+ for(int i=1; i<=6; i++)
+ vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.inLO["+i+"]", (i==1)?0:1);
// set the ILC input to 1
for(int i=1; i<=8; i++) {
vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.\\inLO["+i+"]", (i==1)?0:1);
}
- // pulse ilc[load] and olc[load]
- vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 1);
- vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_", 1);
+ vm.setNodeState("northFif@1.upDown8w@2.weakStag@22.addr1in2@0.fire", 1);
model.waitNS(1000);
- vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 0);
- vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_", 0);
+ vm.setNodeState("northFif@1.upDown8w@2.weakStag@22.addr1in2@0.fire", 0);
model.waitNS(1000);
vm.setNodeState("sid[9]", 1);
vm.setNodeState("sir[9]", 0);
model.waitNS(1000);
+ // pulse ilc[load] and olc[load]
+ vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 1);
+ vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_decLO_", 1);
+ vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_torpLO_", 1);
+ if (!kesselsCounter)
+ vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_", 1);
+ model.waitNS(100);
+ model.waitNS(1);
+ vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_");
+ vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_decLO_");
+ vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_torpLO_");
+ if (!kesselsCounter)
+ vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_");
+
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__set_");
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__clr_");
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__set_");
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__clr_");
+
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__set_");
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__clr_");
+
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@0.net_50");
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@1.net_50");
// loads the C-flag. It will get loaded with an "X",
// which will then leak into the flags and from there the
// predicate.
- //vm.releaseNode("outputDo@0.outM1Pre@0.litDandP@0.latch2in@0.hi2inLat@0.latchKee@0.out_B_");
+ vm.releaseNode("outputDo@0.outM1Pre@0.litDandP@0.latch2in@0.hi2inLat@0.latchKee@0.out_B_");
+ vm.releaseNode("northFif@1.upDown8w@2.weakStag@22.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ONE+1)+"]");
+ vm.releaseNode("northFif@1.upDown8w@2.weakStag@22.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO+1)+"]");
+ vm.releaseNode("northFif@1.upDown8w@2.weakStag@22.addr1in2@0.fire");
- vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_");
for(int i=1; i<=8; i++) {
if (i!=7)
vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.\\inLO["+i+"] ");
}
model.waitNS(1000);
- vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_");
- for(int i=1; i<=6; i++)
- vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.inLO["+i+"]");
+
+ if (!kesselsCounter)
+ for(int i=1; i<=6; i++)
+ vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.inLO["+i+"]");
// the proper stopper states come up in an undefined ("X")
// state, so under Verilog we need to force them to a
//tokOut.resetAfterMasterClear();
instrIn.resetAfterMasterClear();
}
+ public static boolean kesselsCounter = true;
+
/** Get the 6 bit outer loop counter. */
public int getOLC() {
shiftReport(true, false);
- BitVector odd = cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH_ODD).bitReverse().not();
- BitVector even = cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH_EVEN).bitReverse().not();
- BitVector ret = new BitVector(6, "olc");
+ BitVector odd = cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH_ODD).bitReverse();
+ BitVector even = cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH_EVEN).bitReverse();
+ if (!kesselsCounter) {
+ odd = odd.not();
+ even = even.not();
+ }
+ BitVector bv = new BitVector(6, "olc");
for(int i=0; i<3; i++) {
- ret.set(i*2, odd.get(i));
- ret.set(i*2+1, even.get(i));
+ bv.set(i*2, odd.get(i));
+ bv.set(i*2+1, even.get(i));
}
- return (int)ret.toLong();
+ return (int)bv.toLong();
}
/** Get the 7 bit inner loop counter. The MSB is the zero bit.
* The low order 6 bits are the count */
return count.bitReverse().toLong();
}
/** Fill the "North" Fifo ring */
+ public void fillNorthProperStopper() {
+ BitVector data = new BitVector(37, "empty");
+ BitVector addr = new BitVector(14, "empty");
+ for(int i=0; i<data.getNumBits(); i++) data.set(i, false);
+ for(int i=0; i<addr.getNumBits(); i++) addr.set(i, false);
+ fillNorthProperStopper(new MarinaPacket(data, false, addr));
+ }
+ /** Fill the "North" Fifo ring */
public void fillNorthProperStopper(MarinaPacket mp) {
+ prln("inserting into north: " + mp);
this.data.fill(mp.toSingleBitVector());
}
- /** Fill the "South" Fifo ring with instructions */
- public void fillSouthProperStopper(Instruction[] instructions) {
- enableInstructionSend(false);
- enableInstructionRecirculate(false);
- for(Instruction i : instructions)
- instrIn.fill(i);
- enableInstructionSend(true);
- }
/** Enable the transmission of instructions from the instruction
* ring test structure to the EPI FIFO. */
public void enableInstructionSend(boolean b) {
public void enableInstructionCounter(Boolean b) {
instrIn.setGeneralPurposeOutput(b);
}
+
+ public void fillSouthProperStopper(Instruction[] instructions) { fillSouthProperStopper(instructions, false); }
+ public void fillSouthProperStopper(Instruction[] instructions, boolean repeat) {
+ enableInstructionSend(false);
+ enableInstructionRecirculate(true);
+ for(Instruction i : instructions)
+ if (i!=null)
+ instrIn.fill(i);
+ enableInstructionRecirculate(repeat);
+ enableInstructionSend(true);
+ instrIn.run();
+ }
+
}
projects / fleet.git / blobdiff