#ship fifo : Fifo
// dumb configurations
-debug.in: [*] take, deliver;
-memory.inAddrRead: [*] take, deliver;
-memory.inAddrWrite: [*] take, deliver;
-memory.inDataWrite: [*] take, deliver;
-//memory.inCount: [*] take, deliver;
-//memory.inStride: [*] take, deliver;
-fifo.in: [*] take, deliver;
+debug.in: set ilc=*; recv, deliver;
+memory.inAddrRead: set ilc=*; recv, deliver;
+memory.inAddrWrite: set ilc=*; recv, deliver;
+memory.inDataWrite: set ilc=*; recv, deliver;
+//memory.inCount: set ilc=*; recv, deliver;
+//memory.inStride: set ilc=*; recv, deliver;
+fifo.in: set ilc=*; recv, deliver;
// addresses and values to initialize the memory with
-//1: sendto memory.inAddrWrite;
-//4: sendto memory.inCount;
-//1: sendto memory.inStride;
-//11: sendto memory.inDataWrite;
-//12: sendto memory.inDataWrite;
-//13: sendto memory.inDataWrite;
-//14: sendto memory.inDataWrite;
+//1: send to memory.inAddrWrite;
+//4: send to memory.inCount;
+//1: send to memory.inStride;
+//11: send to memory.inDataWrite;
+//12: send to memory.inDataWrite;
+//13: send to memory.inDataWrite;
+//14: send to memory.inDataWrite;
// send write-completion tokens to the fifo output
memory.out:
- load repeat counter with 4; take, notify fifo.out;
- [*] take, sendto debug.in;
+ set ilc=4; collect, send token to fifo.out;
+ set ilc=*; collect, send to debug.in;
// when the write-completion tokens accumulate, unleash
// the read addresses
fifo.out:
- load repeat counter with 4; wait;
- take, sendto memory.inAddrRead;
+ set ilc=4; recv token;
+ collect, send to memory.inAddrRead;
// read addresses
-//4: sendto fifo.in;
-//4: sendto memory.inCount;
-//-1: sendto memory.inStride;
+//4: send to fifo.in;
+//4: send to memory.inCount;
+//-1: send to memory.inStride;