--- /dev/null
+--- gcc/config/mips/mips.md Thu Aug 21 12:04:35 2003
++++ gcc/config/mips/mips.md Thu Aug 21 12:05:59 2003
+@@ -4843,155 +4843,6 @@
+ ;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
+ ;; It isn't clear whether this will give better code.
+
+-;; Only specify the mode operand 1, the rest are assumed to be word_mode.
+-(define_expand "extv"
+- [(set (match_operand 0 "register_operand" "")
+- (sign_extract (match_operand:QI 1 "memory_operand" "")
+- (match_operand 2 "immediate_operand" "")
+- (match_operand 3 "immediate_operand" "")))]
+- "!TARGET_MIPS16"
+- "
+-{
+- /* If the field does not start on a byte boundary, then fail. */
+- if (INTVAL (operands[3]) % 8 != 0)
+- FAIL;
+-
+- /* MIPS I and MIPS II can only handle a 32bit field. */
+- if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
+- FAIL;
+-
+- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
+- if (TARGET_64BIT
+- && INTVAL (operands[2]) != 64
+- && INTVAL (operands[2]) != 32)
+- FAIL;
+-
+- /* This can happen for a 64 bit target, when extracting a value from
+- a 64 bit union member. extract_bit_field doesn't verify that our
+- source matches the predicate, so we force it to be a MEM here. */
+- if (GET_CODE (operands[1]) != MEM)
+- FAIL;
+-
+- /* Change the mode to BLKmode for aliasing purposes. */
+- operands[1] = adjust_address (operands[1], BLKmode, 0);
+- set_mem_size (operands[1], GEN_INT (INTVAL (operands[2]) / BITS_PER_UNIT));
+-
+- /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value. */
+- if (INTVAL (operands[2]) == 64)
+- emit_insn (gen_movdi_uld (operands[0], operands[1]));
+- else
+- {
+- if (TARGET_64BIT)
+- {
+- operands[0] = gen_lowpart (SImode, operands[0]);
+- if (operands[0] == NULL_RTX)
+- FAIL;
+- }
+- emit_insn (gen_movsi_ulw (operands[0], operands[1]));
+- }
+- DONE;
+-}")
+-
+-;; Only specify the mode operand 1, the rest are assumed to be word_mode.
+-(define_expand "extzv"
+- [(set (match_operand 0 "register_operand" "")
+- (zero_extract (match_operand:QI 1 "memory_operand" "")
+- (match_operand 2 "immediate_operand" "")
+- (match_operand 3 "immediate_operand" "")))]
+- "!TARGET_MIPS16"
+- "
+-{
+- /* If the field does not start on a byte boundary, then fail. */
+- if (INTVAL (operands[3]) % 8 != 0)
+- FAIL;
+-
+- /* MIPS I and MIPS II can only handle a 32bit field. */
+- if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
+- FAIL;
+-
+- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
+- if (TARGET_64BIT
+- && INTVAL (operands[2]) != 64
+- && INTVAL (operands[2]) != 32)
+- FAIL;
+-
+- /* This can happen for a 64 bit target, when extracting a value from
+- a 64 bit union member. extract_bit_field doesn't verify that our
+- source matches the predicate, so we force it to be a MEM here. */
+- if (GET_CODE (operands[1]) != MEM)
+- FAIL;
+-
+- /* Change the mode to BLKmode for aliasing purposes. */
+- operands[1] = adjust_address (operands[1], BLKmode, 0);
+- set_mem_size (operands[1], GEN_INT (INTVAL (operands[2]) / BITS_PER_UNIT));
+-
+- /* Otherwise, emit a lwl/lwr pair to load the value. */
+- if (INTVAL (operands[2]) == 64)
+- emit_insn (gen_movdi_uld (operands[0], operands[1]));
+- else
+- {
+- if (TARGET_64BIT)
+- {
+- operands[0] = gen_lowpart (SImode, operands[0]);
+- if (operands[0] == NULL_RTX)
+- FAIL;
+- }
+- emit_insn (gen_movsi_ulw (operands[0], operands[1]));
+- }
+- DONE;
+-}")
+-
+-;; Only specify the mode operands 0, the rest are assumed to be word_mode.
+-(define_expand "insv"
+- [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
+- (match_operand 1 "immediate_operand" "")
+- (match_operand 2 "immediate_operand" ""))
+- (match_operand 3 "register_operand" ""))]
+- "!TARGET_MIPS16"
+- "
+-{
+- /* If the field does not start on a byte boundary, then fail. */
+- if (INTVAL (operands[2]) % 8 != 0)
+- FAIL;
+-
+- /* MIPS I and MIPS II can only handle a 32bit field. */
+- if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
+- FAIL;
+-
+- /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
+- if (TARGET_64BIT
+- && INTVAL (operands[1]) != 64
+- && INTVAL (operands[1]) != 32)
+- FAIL;
+-
+- /* This can happen for a 64 bit target, when storing into a 32 bit union
+- member. store_bit_field doesn't verify that our target matches the
+- predicate, so we force it to be a MEM here. */
+- if (GET_CODE (operands[0]) != MEM)
+- FAIL;
+-
+- /* Change the mode to BLKmode for aliasing purposes. */
+- operands[0] = adjust_address (operands[0], BLKmode, 0);
+- set_mem_size (operands[0], GEN_INT (INTVAL (operands[1]) / BITS_PER_UNIT));
+-
+- /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value. */
+- if (INTVAL (operands[1]) == 64)
+- emit_insn (gen_movdi_usd (operands[0], operands[3]));
+- else
+- {
+- if (TARGET_64BIT)
+- {
+- operands[3] = gen_lowpart (SImode, operands[3]);
+- if (operands[3] == NULL_RTX)
+- FAIL;
+- }
+- emit_insn (gen_movsi_usw (operands[0], operands[3]));
+- }
+- DONE;
+-}")
+-
+-;; unaligned word moves generated by the bit field patterns
+-
+ (define_insn "movsi_ulw"
+ [(set (match_operand:SI 0 "register_operand" "=&d,&d")
+ (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")]
+--- gcc/config/mips/mips.c Fri Jan 31 15:51:23 2003
++++ gcc/config/mips/mips.c Thu Aug 21 20:04:19 2003
+@@ -4027,34 +4027,6 @@
+ bytes -= 8;
+ }
+
+- /* ??? Fails because of a MIPS assembler bug? */
+- else if (TARGET_64BIT && bytes >= 8
+- && ! TARGET_SR71K
+- && ! TARGET_MIPS16)
+- {
+- if (BYTES_BIG_ENDIAN)
+- {
+- load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
+- load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
+- load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
+- load_store[num].last_store = "sdr\t%0,%2";
+- load_store[num].final = "sdl\t%0,%1";
+- }
+- else
+- {
+- load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
+- load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
+- load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
+- load_store[num].last_store = "sdr\t%0,%1";
+- load_store[num].final = "sdl\t%0,%2";
+- }
+-
+- load_store[num].mode = DImode;
+- offset += 8;
+- bytes -= 8;
+- use_lwl_lwr = 1;
+- }
+-
+ else if (bytes >= 4 && align >= 4)
+ {
+ load_store[num].load = "lw\t%0,%1";
+@@ -4065,33 +4037,6 @@
+ load_store[num].mode = SImode;
+ offset += 4;
+ bytes -= 4;
+- }
+-
+- else if (bytes >= 4
+- && ! TARGET_SR71K
+- && ! TARGET_MIPS16)
+- {
+- if (BYTES_BIG_ENDIAN)
+- {
+- load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
+- load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
+- load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
+- load_store[num].last_store = "swr\t%0,%2";
+- load_store[num].final = "swl\t%0,%1";
+- }
+- else
+- {
+- load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
+- load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
+- load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
+- load_store[num].last_store = "swr\t%0,%1";
+- load_store[num].final = "swl\t%0,%2";
+- }
+-
+- load_store[num].mode = SImode;
+- offset += 4;
+- bytes -= 4;
+- use_lwl_lwr = 1;
+ }
+
+ else if (bytes >= 2 && align >= 2)
projects / org.ibex.core.git / blobdiff