projects / fleet.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b6d4186) | patch
add DDR2 controller, generated via MIG
authormegacz <adam@megacz.com>
Sun, 1 Mar 2009 22:06:32 +0000 (14:06 -0800)
committermegacz <adam@megacz.com>
Sun, 1 Mar 2009 22:06:32 +0000 (14:06 -0800)
commit0e179ecc6a0cd616fbc633aa97530c76a33ba4c7
treebbf1ae564961c094c898cb2d4c57f22c6d8ea009tree | snapshot
parentb6d4186610898c3e2e84738fe3b344cb83c79ca5commit | diff
add DDR2 controller, generated via MIG
27 files changed:
Makefile diff | blob | history
ships/DDR2.ship diff | blob | history
ships/DDR2.ship- [new file with mode: 0644] blob
ships/Dvi.ship diff | blob | history
src/edu/berkeley/fleet/fpga/Fpga.java diff | blob | history
src/edu/berkeley/fleet/fpga/ddr2/ddr2_chipscope.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_ctrl.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_idelay_ctrl.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_infrastructure.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_mem_if_top.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dm_iob.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dqs_iob.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_init.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_io.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_top.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_write.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_sdram.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_top.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_usr_addr_fifo.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_usr_rd.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_usr_top.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/ddr2/ddr2_usr_wr.v [new file with mode: 0644] blob
src/edu/berkeley/fleet/fpga/main.ucf diff | blob | history
src/edu/berkeley/fleet/fpga/main.ucf- [new file with mode: 0644] blob
The FleetCode -- http://fleet.cs.berkeley.edu/