public static void main(String[] s) throws Exception {
new Fpga(new Module("root")).top.dump(s[0]);
+ PrintWriter pw;
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v")));
+ pw.println("`timescale 1ns / 10ps");
+ pw.close();
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
+ pw.println("`define BRAM_ADDR_WIDTH 14");
+ pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH");
+ pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
+ pw.println("`define BRAM_NAME bram14");
+ pw.println("`include \"bram.inc\"");
+ pw.close();
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/vram.v")));
+ pw.println("`define BRAM_ADDR_WIDTH 19");
+ pw.println("`define BRAM_DATA_WIDTH 3");
+ pw.println("`define BRAM_SIZE (640*480)");
+ pw.println("`define BRAM_NAME vram");
+ pw.println("`include \"bram.inc\"");
+ pw.close();
}
public Module getVerilogModule() { return top; }
+++ /dev/null
-`define BRAM_ADDR_WIDTH 14
-`define BRAM_DATA_WIDTH `DATAWIDTH
-`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))
-`define BRAM_NAME bram14
-
-`include "bram.inc"