== Ports ===========================================================
data in: in
data in: inOp
+data in: inOp.x
+data in: inOp.y
+data in: inOp.z
data out: out
== FleetSim ==============================================================
== FPGA ==============================================================
reg have_a;
- reg [(`DATAWIDTH-1):0] reg_a;
+ reg [(`PACKET_WIDTH-1):0] reg_a;
reg have_op;
- reg [(`DATAWIDTH-1):0] reg_op;
+ reg [(`PACKET_WIDTH-1):0] reg_op;
+ reg [(`PACKET_WIDTH-1):0] extrabits;
always @(posedge clk) begin
if (!have_a) begin
`onread(in_r, in_a) have_a = 1; reg_a = in_d; end
end
if (!have_op) begin
- `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
+ `onread(inOp_r, inOp_a)
+ have_op = 1;
+ reg_op = inOp_d[(`DATAWIDTH-1):0];
+ extrabits = inOp_d[(`PACKET_WIDTH-1):`DATAWIDTH];
end
+ end
if (have_a && have_op) begin
case (reg_op)
2: out_d = reg_a-1;
3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
4: out_d = 37'b1111111111111111111111111111111111111;
+ 5: out_d = extrabits;
default: out_d = 0;
endcase
`onwrite(out_r, out_a)
== FPGA ==============================================================
- // FIXME
-/*
- reg have_a;
- reg [(`DATAWIDTH-1):0] reg_a;
- reg have_b;
- reg [(`DATAWIDTH-1):0] reg_b;
- reg have_op;
- reg [(`DATAWIDTH-1):0] reg_op;
+ reg have_in1;
+ reg [(`DATAWIDTH-1):0] reg_in1;
+ reg have_in2;
+ reg [(`DATAWIDTH-1):0] reg_in2;
+ reg have_in;
+ reg [(`PACKET_WIDTH-1):0] reg_in;
+ reg have_out1;
+ reg have_out2;
+ reg fire;
always @(posedge clk) begin
- if (!have_a) begin
- `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
+ if (!have_in1) begin
+ `onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
end
- if (!have_b) begin
- `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
+ if (!have_in2) begin
+ `onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
end
- if (!have_op) begin
- `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
+ if (!have_in) begin
+ `onread(in_r, in_a) have_in = 1; reg_in = in_d; end
end
-
- if (have_a && have_b && have_op) begin
- case (reg_op)
- 0: out_d = reg_a + reg_b;
- 1: out_d = reg_a - reg_b;
- default: out_d = 0;
- endcase
- `onwrite(out_r, out_a)
- have_a = 0;
- have_b = 0;
- have_op = 0;
+
+ if (have_out1) begin
+ `onwrite(out1_r, out1_d) have_out1 = 0; end
+ end
+ if (have_out2) begin
+ `onwrite(out2_r, out2_d) have_out2 = 0; end
+ end
+
+ if (have_in && !have_out1 && !have_out2) begin
+ case (reg_in[`PACKET_WIDTH-1:`DATAWIDTH])
+ 00: /* in.swapIfZero */ fire = reg_in[`DATAWIDTH-1:0] == 0;
+ 06: /* in.muxIfZero */ fire = reg_in[`DATAWIDTH-1:0] == 0;
+ 12: /* in.deMuxIfZero */ fire = reg_in[`DATAWIDTH-1:0] == 0;
+ 01: /* in.swapIfNonZero */ fire = reg_in[`DATAWIDTH-1:0] != 0;
+ 07: /* in.muxIfNonZero */ fire = reg_in[`DATAWIDTH-1:0] != 0;
+ 13: /* in.deMuxIfNonZero */ fire = reg_in[`DATAWIDTH-1:0] != 0;
+ 02: /* in.swapIfNegative */ fire = reg_in[`DATAWIDTH-1:0] < 0;
+ 08: /* in.muxIfNegative */ fire = reg_in[`DATAWIDTH-1:0] < 0;
+ 14: /* in.deMuxIfNegative */ fire = reg_in[`DATAWIDTH-1:0] < 0;
+ 03: /* in.swapIfPositive */ fire = reg_in[`DATAWIDTH-1:0] > 0;
+ 09: /* in.muxIfPositive */ fire = reg_in[`DATAWIDTH-1:0] > 0;
+ 15: /* in.deMuxIfPositive */ fire = reg_in[`DATAWIDTH-1:0] > 0;
+ 04: /* in.swapIfNonNegative */ fire = reg_in[`DATAWIDTH-1:0] >= 0;
+ 16: /* in.deMuxIfNonNegative */ fire = reg_in[`DATAWIDTH-1:0] >= 0;
+ 10: /* in.muxIfNonNegative */ fire = reg_in[`DATAWIDTH-1:0] >= 0;
+ 05: /* in.swapIfNonPositive */ fire = reg_in[`DATAWIDTH-1:0] <= 0;
+ 11: /* in.muxIfNonPositive */ fire = reg_in[`DATAWIDTH-1:0] <= 0;
+ 17: /* in.deMuxIfNonPositive */ fire = reg_in[`DATAWIDTH-1:0] <= 0;
+ endcase
+
+ if (reg_in[`PACKET_WIDTH-1:`DATAWIDTH] <= 5) begin
+ if (have_in1 && have_in2) begin
+ have_out1 = 1;
+ have_out2 = 1;
+ have_in1 = 0;
+ have_in2 = 0;
+ out1_d = fire ? reg_in2 : reg_in1;
+ out2_d = fire ? reg_in1 : reg_in2;
+ end
+ end else if (reg_in[`PACKET_WIDTH-1:`DATAWIDTH] <= 11) begin
+ if (fire && have_in2) begin
+ have_out1 = 1;
+ have_in2 = 0;
+ out1_d = in2_d;
+ end else if (!fire && have_in1) begin
+ have_out1 = 1;
+ have_in1 = 0;
+ out1_d = in1_d;
+ end
+ end else begin
+ if (have_in1) begin
+ if (fire) begin
+ have_out2 = 1;
+ out2_d = in1_d;
+ have_in1 = 0;
+ end else begin
+ have_out1 = 1;
+ out1_d = in1_d;
+ have_in1 = 0;
+ end
+ end
end
- end
+ end
end
-*/
);
input clk;
- `input(in_addr_r, in_addr_a, in_addr_a_, [(`DATAWIDTH-1):0], in_addr_d)
+ `input(in_addr_r, in_addr_a, in_addr_a_, [(2+`DATAWIDTH-1):0], in_addr_d)
`input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
`input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d)
`input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d)
- `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
- `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
+ `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
+ //`defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
`input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
`input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
reg [(`INSTRUCTION_WIDTH-1):0] command;
reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
reg send_done;
+ reg send_read;
reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
reg [(`DATAWIDTH-1):0] data;
initial launched = 0;
some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
+ assign out_d_ = ramread;
always @(posedge clk) begin
send_done <= 0;
end
- end else if (in_addr_r && write_data_r) begin
- in_addr_a = 1;
+ end else if (send_read) begin
+ `onwrite(out_r, out_a)
+ send_read <= 0;
+ end
+
+ end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
+ in_addr_a = 1;
+ send_read <= 1;
+ current_instruction_read_from <= in_addr_d[(`DATAWIDTH-1):0];
+
+ end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
+ in_addr_a = 1;
write_data_a = 1;
send_done <= 1;
write_flag <= 1;
- in_addr <= in_addr_d;
+ in_addr <= in_addr_d[(`DATAWIDTH-1):0];
write_data <= write_data_d;
end else if (ihorn_full && launched) begin
} else if (command.equals("test")) {
test(fleet, new File(args.get(0)));
+ } else if (command.equals("asm")) {
+ String filename = args.get(0);
+ FileOutputStream out = new FileOutputStream("fleet.fo");
+ Reader r = new InputStreamReader(new FileInputStream(args.get(0)));
+ edu.berkeley.fleet.assembler.Main.assemble(fleet, r, out);
+ out.flush();
} else {
usage();
new Slipway().dumpFabric(false);
}
- public Slipway() { this("valentine.bit"); }
+ public Slipway() { this("groundhog.bit"); }
public Slipway(String bitfile) {
this.bitfile = bitfile;
createShip("Debug", "debug");
createShip("Alu2", "alu2a");
createShip("Alu2", "alu2b");
- //createShip("Alu2", "alu2c");
- //createShip("Alu2", "alu2d");
+ createShip("Alu2", "alu2c");
+ createShip("Alu2", "alu2d");
createShip("Execute", "execute");
createShip("Fifo", "fifo1");
createShip("Fifo", "fifo2");
- //createShip("Fifo", "fifo3");
- //createShip("Fifo", "fifo4");
+ createShip("Fifo", "fifo3");
+ createShip("Fifo", "fifo4");
+ createShip("Memory", "Memory");
createShip("Memory", "Memory");
- //createShip("Memory", "Memory");
createShip("Lut3", "lut3");
createShip("Alu1", "alu1");
createShip("Choice", "Choice");
} else if (prefix.equals("dest")) {
p.addr = addr;
p.bits = bits;
- int count = 1;
+ int count = 0;
for(Destination d : p.getDestinations()) {
if (!(d instanceof SlipwayBenkoBox.VirtualPort)) continue;
SlipwayBenkoBox.VirtualPort vp = (SlipwayBenkoBox.VirtualPort)d;
- vp.addr = p.addr | (count << (bits+1));
+ vp.addr = p.addr | (count << bits);
count++;
}
}
FileOutputStream out = new FileOutputStream(outf);
PrintWriter pw = new PrintWriter(out);
- boolean auto = filename.equals("alu2") || filename.equals("alu1") || filename.equals("lut3");
+ boolean auto = filename.equals("alu2") || filename.equals("alu1") || filename.equals("lut3") || filename.equals("choice");
if (auto) {
pw.println("`include \"macros.v\"");
pw.println();
bb_name+"_r, "+
bb_name+"_a, "+
bb_name+"_a_, "+
- "[(`DATAWIDTH-1):0],"+
+ "[(`PACKET_WIDTH-1):0],"+
bb_name+"_d)"
);
} else {
bb_name+"_r, "+
bb_name+"_r_, "+
bb_name+"_a, "+
- "[(`DATAWIDTH-1):0],"+
+ "[(`PACKET_WIDTH-1):0],"+
bb_name+"_d_)"
);
pw.println("`defreg(" +
bb_name+"_d_, "+
- "[(`DATAWIDTH-1):0],"+
+ "[(`PACKET_WIDTH-1):0],"+
bb_name+"_d)"
);
}
private final String name;
private final SlipwayShip ship;
- private final Destination[] ports;
+ private Destination[] ports;
public Iterable<Destination> getDestinations() {
- HashSet<Destination> ret = new HashSet<Destination>();
+ ArrayList<Destination> ret = new ArrayList<Destination>();
for(Destination d : ports) ret.add(d);
return ret;
}
ship.addBenkoBox(name, this);
}
+ public void addDestination(String dest) {
+ Destination[] newports = new Destination[ports.length+1];
+ System.arraycopy(ports, 0, newports, 0, ports.length);
+ newports[newports.length-1] = new VirtualPort(dest);
+ ports = newports;
+ }
public class VirtualPort extends Destination {
public String name;
/** You should instantiate a bunch of Inboxes and Outboxes in your constructor */
public SlipwayShip(Slipway fleet, String name, String type, ShipDescription sd) {
this.fleet = fleet; this.type = type;
- for(BenkoBoxDescription sdbb : sd)
- new SlipwayBenkoBox(sdbb.isInbox(), this, sdbb.getName());
+ for(BenkoBoxDescription sdbb : sd) {
+ SlipwayBenkoBox sbb = new SlipwayBenkoBox(sdbb.isInbox(), this, sdbb.getName());
+ for(String port : sdbb) {
+ if (port.equals("")) continue;
+ sbb.addDestination(port);
+ }
+ }
if (type.equals("Debug")) {
new SlipwayBenkoBox(false, this, "out", true);
end
if (`instruction_bit_latch(instruction)) begin
`packet_data(`data_out_d) = `data_in_d;
+ `extra
end
fire_ok = 1;
end
input [(`PACKET_WIDTH-1):0] fabric_in_d;
`output(fabric_out_r, fabric_out_r_, fabric_out_a, [(`PACKET_WIDTH-1):0], fabric_out_d_)
`defreg(fabric_out_d_, [(`PACKET_WIDTH-1):0], fabric_out_d)
- `output(ship_r, ship_r_, ship_a, [(`DATAWIDTH-1):0], ship_d_)
+ `output(ship_r, ship_r_, ship_a, [(`PACKET_WIDTH-1):0], ship_d_)
reg [(`PACKET_WIDTH-1):0] ship_d;
- assign ship_d_ = `packet_data(ship_d);
+ assign ship_d_ = { `packet_dest(ship_d), `packet_data(ship_d) };
`input(instr_r, instr_a, instr_a_, [(`INSTRUCTION_WIDTH-1):0], instr_d)
fifo4 dfifo(clk, fabric_in_r, fabric_in_a_, fabric_in_d,
fabric_in_r0, fabric_in_a0_, fabric_in_d0);
+ `define extra `packet_dest(`data_out_d) = `packet_dest(fabric_in_d0);
`include "box.inc"
endmodule
fifo4 dfifo(clk, fabric_in_r, fabric_in_a_, fabric_in_d,
fabric_in_r0, fabric_in_a0_, fabric_in_d0);
+ `define extra
`include "box.inc"
endmodule
projects / fleet.git / commitdiff