== FPGA ==============================================================
// FIXME
+/*
reg have_a;
reg [(`DATAWIDTH-1):0] reg_a;
reg have_b;
end
end
end
-
+*/
+++ /dev/null
-ship: Dscratch
-
-== Ports ===========================================================
-data in: inReadAddr
-data out: outReadData
-
-data in: inWriteAddr
-data in: inWriteData
-token out: outWriteDone
-
-== Fleeterpreter ====================================================
- private long[] mem = new long[0];
- public long readMem(int addr) { return mem[addr]; }
- public void writeMem(int addr, long val) {
- if (addr >= mem.length) {
- long[] newmem = new long[addr * 2 + 1];
- System.arraycopy(mem, 0, newmem, 0, mem.length);
- mem = newmem;
- }
- mem[addr] = val;
- }
-
- public void service() {
- if (box_inReadAddr.dataReadyForShip() &&
- box_outReadData.readyForItemFromShip()) {
- box_outReadData.addDataFromShip(readMem((int)box_inReadAddr.removeDataForShip()));
- }
-
- if (box_inWriteAddr.dataReadyForShip() &&
- box_inWriteData.dataReadyForShip() &&
- box_outWriteDone.readyForItemFromShip()) {
- writeMem((int)box_inWriteAddr.removeDataForShip(),
- box_inWriteData.removeDataForShip());
- box_outWriteDone.addDataFromShip(0);
- }
- }
-
-== FleetSim ==============================================================
-
-== FPGA ==============================================================
-`include "macros.v"
-`define BRAM_ADDR_WIDTH 14
-`define BRAM_DATA_WIDTH `DATAWIDTH
-`define BRAM_NAME dscratch_bram
-`include "bram.inc"
-
-module dscratch (clk,
- read_addr_r, read_addr_a_, read_addr_d,
- read_data_r_, read_data_a, read_data_d_,
- write_addr_r, write_addr_a_, write_addr_d,
- write_data_r, write_data_a_, write_data_d,
- write_done_r_, write_done_a, write_done_d_
- );
-
- input clk;
- `input(read_addr_r, read_addr_a, read_addr_a_, [(`DATAWIDTH-1):0], read_addr_d)
- `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_)
- `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d)
-
- `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
- `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
- `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
- `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
-
- reg bram_we;
- wire bram_we_;
- assign bram_we_ = bram_we;
- wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data;
- reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address;
- wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address;
- reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data;
- wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_;
- assign bram_write_data_ = bram_write_data;
- `BRAM_NAME mybram(clk,
- bram_we_, bram_write_address,
- bram_read_address, bram_write_data_,
- not_connected, bram_read_data);
-
- reg send_done;
-
- reg have_read; initial have_read = 0;
- reg read_pending; initial read_pending = 0;
- assign bram_read_address = read_addr_d;
-
- always @(posedge clk) begin
- bram_we = 0;
- if (send_done) begin
- `onwrite(write_done_r, write_done_a)
- send_done = 0;
- end
- end else begin
- if (!write_addr_r && write_addr_a) write_addr_a = 0;
- if (!write_data_r && write_data_a) write_data_a = 0;
- if (write_addr_r && write_data_r) begin
- write_addr_a = 1;
- write_data_a = 1;
- bram_we = 1;
- send_done = 1;
- bram_write_address = write_addr_d;
- bram_write_data = write_data_d;
- end
- end
-
- if (read_pending) begin
- read_pending <= 0;
- have_read <= 1;
- read_data_d <= bram_read_data;
- end else if (have_read) begin
- `onwrite(read_data_r, read_data_a)
- have_read <= 0;
- end
- end else begin
- `onread(read_addr_r, read_addr_a)
- // ======= Careful with the timing here! =====================
- // We MUST capture bram_read_data on the very next clock since
- // read_addr_d is free to change after the next clock
- // ===========================================================
- read_pending <= 1;
- end
- end
-
- end
-
-endmodule
-
-
-== Constants ========================================================
-== TeX ==============================================================
-
-== Contributors =========================================================
-Adam Megacz <megacz@cs.berkeley.edu>
+++ /dev/null
-ship: Iscratch
-
-== Ports ===========================================================
-data in: inWriteAddr
-data in: inWriteData
-token out: outWriteDone
-
-data in: inCBD
-
-== Fleeterpreter ====================================================
-
- private long[] mem = new long[0];
- public long readMem(int addr) { return mem[addr]; }
- public void writeMem(int addr, long val) {
- if (addr >= mem.length) {
- long[] newmem = new long[addr * 2 + 1];
- System.arraycopy(mem, 0, newmem, 0, mem.length);
- mem = newmem;
- }
- mem[addr] = val;
- }
-
- public void dispatch(int addr, int size) {
- for(int i=addr; i<addr+size; i++) {
- Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
- ((Interpreter)getFleet()).dispatch(instr, i);
- }
- }
-
- public void service() {
- if (box_inCBD.dataReadyForShip()) {
- long val = box_inCBD.removeDataForShip();
- long addr = val >> 6;
- long size = val & 0x3f;
- dispatch((int)addr, (int)size);
- }
-
- if (box_inWriteAddr.dataReadyForShip() &&
- box_inWriteData.dataReadyForShip() &&
- box_outWriteDone.readyForItemFromShip()) {
- Interpreter f = (Interpreter)getFleet();
- writeMem((int)box_inWriteAddr.removeDataForShip(),
- box_inWriteData.removeDataForShip());
- box_outWriteDone.addDataFromShip(0);
- }
- }
-
- public void boot(byte[] instructions) {
- Interpreter fleet = (Interpreter)getFleet();
- // load the iscratch and take note of the 0-address INCBD
- long launch = 0;
- for(int i=0; i<instructions.length; i+=6) {
- long word = 0;
- for(int j=0; j<6; j++)
- word = (word << 8) | (instructions[i+j] & 0xff);
- writeMem(i/6, word);
- if (i==0) launch = word;
- }
-
- // dispatch the 0-address INCBD
- int base = (int)(launch >> 6);
- base = base & ~(0xffffffff << 18);
- int size = (int)launch;
- size = size & ~(0xffffffff << 6);
- dispatch(base, size);
- }
-
-== Constants ========================================================
-== TeX ==============================================================
-== FleetSim ==============================================================
-== FPGA ==============================================================
-`include "macros.v"
-`define BRAM_ADDR_WIDTH 14
-`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
-`define BRAM_NAME iscratch_bram
-`include "bram.inc"
-
-module iscratch (clk,
- write_addr_r, write_addr_a_, write_addr_d,
- write_data_r, write_data_a_, write_data_d,
- write_done_r_, write_done_a, write_done_d_,
- cbd_r, cbd_a_, cbd_d,
- preload_r, preload_a_, preload_d,
- ihorn_r_, ihorn_a, ihorn_d_,
- dhorn_r_, dhorn_a, dhorn_d_
- );
-
- input clk;
- `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
- `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
- `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
- `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
-
- `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
- `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
- `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
- `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
- `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
- `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
-
- reg ihorn_full;
- initial ihorn_full = 0;
- reg dhorn_full;
- initial dhorn_full = 0;
- reg command_valid;
- initial command_valid = 0;
-
- reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
- reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
- initial preload_size = 0;
-
- reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
- reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
- reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
- reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
- reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
- reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
- reg [(`INSTRUCTION_WIDTH-1):0] command;
- reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
- reg send_done;
-
- reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
- reg [(`DATAWIDTH-1):0] data;
-
- reg write_flag;
- reg [(`BRAM_ADDR_WIDTH-1):0] write_addr;
- reg [(`BRAM_DATA_WIDTH-1):0] write_data;
-
- wire [(`BRAM_DATA_WIDTH-1):0] ramread;
-
- reg command_valid_read;
- initial command_valid_read = 0;
-
- reg launched;
- initial launched = 0;
-
- iscratch_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
-
- always @(posedge clk) begin
-
- write_flag <= 0;
-
- if (!write_addr_r && write_addr_a) write_addr_a = 0;
- if (!write_data_r && write_data_a) write_data_a = 0;
-
- if (command_valid_read) begin
- command_valid_read <= 0;
- command_valid <= 1;
-
- end else if (send_done) begin
- `onwrite(write_done_r, write_done_a)
- send_done <= 0;
- end
-
- end else if (write_addr_r && write_data_r) begin
- write_addr_a = 1;
- write_data_a = 1;
- send_done <= 1;
- write_flag <= 1;
- write_addr <= write_addr_d;
- write_data <= write_data_d;
-
- end else if (ihorn_full && launched) begin
- `onwrite(ihorn_r, ihorn_a)
- ihorn_full <= 0;
- end
-
- end else if (dhorn_full) begin
- `onwrite(dhorn_r, dhorn_a)
- dhorn_full <= 0;
- end
-
- end else if (command_valid) begin
- command_valid <= 0;
- command = ramread;
- case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
- 0: begin
- ihorn_full <= 1;
- ihorn_d <= command;
- end
- 1: begin
- dhorn_full <= 1;
- temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
- temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
- data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
- data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
- `packet_data(dhorn_d) <= temp;
- `packet_dest(dhorn_d) <=
- command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
- end
- 2: begin
- dhorn_full <= 1;
- `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
- `packet_dest(dhorn_d) <= command[34:24];
- end
- 3: begin
- dhorn_full <= 1;
- `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
- `packet_dest(dhorn_d) <= command[34:24];
- end
- endcase
-
- end else if (cbd_pos < cbd_size) begin
- current_instruction_read_from <= cbd_base+cbd_pos;
- command_valid_read <= 1;
- cbd_pos <= cbd_pos + 1;
-
- end else begin
- `onread(cbd_r, cbd_a)
- cbd_pos <= 0;
- cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
- cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
-
- end else begin
- `onread(preload_r, preload_a)
- if (preload_size == 0) begin
- preload_size <= preload_d;
- end else if (!launched) begin
- write_flag <= 1;
- write_data <= preload_d;
- write_addr <= preload_pos;
- if (preload_pos == 0) begin
- temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
- temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
- end
- if ((preload_pos+1) == preload_size) begin
- cbd_pos <= 0;
- cbd_base <= temp_base;
- cbd_size <= temp_size;
- launched <= 1;
- end
- preload_pos <= preload_pos + 1;
- end
- end
- end
- end
- end
-endmodule
-
-
-
-
-
-== Contributors =========================================================
-Adam Megacz <megacz@cs.berkeley.edu>
== FPGA ==============================================================
`include "macros.v"
`define BRAM_ADDR_WIDTH 14
-`define BRAM_DATA_WIDTH `DATAWIDTH
-`define BRAM_NAME dscratch_bram
+`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
+`define BRAM_NAME some_bram
`include "bram.inc"
-module dscratch (clk,
- read_addr_r, read_addr_a_, read_addr_d,
- read_data_r_, read_data_a, read_data_d_,
- write_addr_r, write_addr_a_, write_addr_d,
+module memory (clk,
+ cbd_r, cbd_a_, cbd_d,
+ in_addr_r, in_addr_a_, in_addr_d,
write_data_r, write_data_a_, write_data_d,
- write_done_r_, write_done_a, write_done_d_
+ stride_r, stride_a_, stride_d,
+ count_r, count_a_, count_d,
+ out_r_, out_a, out_d_,
+ preload_r, preload_a_, preload_d,
+ ihorn_r_, ihorn_a, ihorn_d_,
+ dhorn_r_, dhorn_a, dhorn_d_
);
input clk;
- `input(read_addr_r, read_addr_a, read_addr_a_, [(`DATAWIDTH-1):0], read_addr_d)
- `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_)
- `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d)
-
- `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
- `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
- `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
- `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
-
- reg bram_we;
- wire bram_we_;
- assign bram_we_ = bram_we;
- wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data;
- reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address;
- wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address;
- reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data;
- wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_;
- assign bram_write_data_ = bram_write_data;
- `BRAM_NAME mybram(clk,
- bram_we_, bram_write_address,
- bram_read_address, bram_write_data_,
- not_connected, bram_read_data);
-
- reg send_done;
-
- reg have_read; initial have_read = 0;
- reg read_pending; initial read_pending = 0;
- assign bram_read_address = read_addr_d;
+ `input(in_addr_r, in_addr_a, in_addr_a_, [(`DATAWIDTH-1):0], in_addr_d)
+ `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
+ `input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d)
+ `input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d)
+ `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
+ `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
+
+ `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
+ `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
+ `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
+ `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
+ `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
+ `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
+
+ reg ihorn_full;
+ initial ihorn_full = 0;
+ reg dhorn_full;
+ initial dhorn_full = 0;
+ reg command_valid;
+ initial command_valid = 0;
+
+ reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
+ reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
+ initial preload_size = 0;
+
+ reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
+ reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
+ reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
+ reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
+ reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
+ reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
+ reg [(`INSTRUCTION_WIDTH-1):0] command;
+ reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
+ reg send_done;
+
+ reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
+ reg [(`DATAWIDTH-1):0] data;
+
+ reg write_flag;
+ reg [(`BRAM_ADDR_WIDTH-1):0] in_addr;
+ reg [(`BRAM_DATA_WIDTH-1):0] write_data;
+
+ wire [(`BRAM_DATA_WIDTH-1):0] ramread;
+
+ reg command_valid_read;
+ initial command_valid_read = 0;
+
+ reg launched;
+ initial launched = 0;
+
+ some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
always @(posedge clk) begin
- bram_we = 0;
- if (send_done) begin
- `onwrite(write_done_r, write_done_a)
- send_done = 0;
+
+ write_flag <= 0;
+
+ if (!in_addr_r && in_addr_a) in_addr_a = 0;
+ if (!write_data_r && write_data_a) write_data_a = 0;
+
+ if (command_valid_read) begin
+ command_valid_read <= 0;
+ command_valid <= 1;
+
+ end else if (send_done) begin
+ `onwrite(out_r, out_a)
+ send_done <= 0;
end
- end else begin
- if (!write_addr_r && write_addr_a) write_addr_a = 0;
- if (!write_data_r && write_data_a) write_data_a = 0;
- if (write_addr_r && write_data_r) begin
- write_addr_a = 1;
- write_data_a = 1;
- bram_we = 1;
- send_done = 1;
- bram_write_address = write_addr_d;
- bram_write_data = write_data_d;
+
+ end else if (in_addr_r && write_data_r) begin
+ in_addr_a = 1;
+ write_data_a = 1;
+ send_done <= 1;
+ write_flag <= 1;
+ in_addr <= in_addr_d;
+ write_data <= write_data_d;
+
+ end else if (ihorn_full && launched) begin
+ `onwrite(ihorn_r, ihorn_a)
+ ihorn_full <= 0;
end
- end
- if (read_pending) begin
- read_pending <= 0;
- have_read <= 1;
- read_data_d <= bram_read_data;
- end else if (have_read) begin
- `onwrite(read_data_r, read_data_a)
- have_read <= 0;
+ end else if (dhorn_full) begin
+ `onwrite(dhorn_r, dhorn_a)
+ dhorn_full <= 0;
end
+
+ end else if (command_valid) begin
+ command_valid <= 0;
+ command = ramread;
+ case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+ 0: begin
+ ihorn_full <= 1;
+ ihorn_d <= command;
+ end
+ 1: begin
+ dhorn_full <= 1;
+ temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
+ temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
+ data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
+ data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
+ `packet_data(dhorn_d) <= temp;
+ `packet_dest(dhorn_d) <=
+ command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
+ end
+ 2: begin
+ dhorn_full <= 1;
+ `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
+ `packet_dest(dhorn_d) <= command[34:24];
+ end
+ 3: begin
+ dhorn_full <= 1;
+ `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
+ `packet_dest(dhorn_d) <= command[34:24];
+ end
+ endcase
+
+ end else if (cbd_pos < cbd_size) begin
+ current_instruction_read_from <= cbd_base+cbd_pos;
+ command_valid_read <= 1;
+ cbd_pos <= cbd_pos + 1;
+
end else begin
- `onread(read_addr_r, read_addr_a)
- // ======= Careful with the timing here! =====================
- // We MUST capture bram_read_data on the very next clock since
- // read_addr_d is free to change after the next clock
- // ===========================================================
- read_pending <= 1;
+ `onread(cbd_r, cbd_a)
+ cbd_pos <= 0;
+ cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
+ cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
+
+ end else begin
+ `onread(preload_r, preload_a)
+ if (preload_size == 0) begin
+ preload_size <= preload_d;
+ end else if (!launched) begin
+ write_flag <= 1;
+ write_data <= preload_d;
+ in_addr <= preload_pos;
+ if (preload_pos == 0) begin
+ temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
+ temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
+ end
+ if ((preload_pos+1) == preload_size) begin
+ cbd_pos <= 0;
+ cbd_base <= temp_base;
+ cbd_size <= temp_size;
+ launched <= 1;
+ end
+ preload_pos <= preload_pos + 1;
+ end
+ end
end
end
-
end
-
endmodule
+
+
+
+
+
== Constants ========================================================
== TeX ==============================================================
createShip("Debug", "debug");
createShip("Alu2", "alu2a");
createShip("Alu2", "alu2b");
- createShip("Alu2", "alu2c");
- createShip("Alu2", "alu2d");
+ //createShip("Alu2", "alu2c");
+ //createShip("Alu2", "alu2d");
createShip("Execute", "execute");
createShip("Fifo", "fifo1");
createShip("Fifo", "fifo2");
- createShip("Fifo", "fifo3");
- createShip("Fifo", "fifo4");
- // FIXME cant have less than two feeding the instruction horn or BUG
- createShip("Iscratch", "iscratch1");
- createShip("Iscratch", "iscratch2");
- createShip("Dscratch", "dscratch1");
- createShip("Dscratch", "dscratch2");
+ //createShip("Fifo", "fifo3");
+ //createShip("Fifo", "fifo4");
+ createShip("Memory", "Memory");
+ //createShip("Memory", "Memory");
createShip("Lut3", "lut3");
createShip("Alu1", "alu1");
+ createShip("Choice", "Choice");
+ createShip("Choice", "Choice");
+ createShip("Choice", "Choice");
+ createShip("Choice", "Choice");
dumpFabric(true);
}
if (quiet) return;
System.out.println("`include \"macros.v\"");
- System.out.println("module fabric(clk, data_Iscratch0_command_r, data_Iscratch0_command_a, data_Iscratch0_command,");
+ System.out.println("module fabric(clk, data_Memory0_command_r, data_Memory0_command_a, data_Memory0_command,");
System.out.println(" data_Debug0_out_r, data_Debug0_out_a, data_Debug0_out);");
System.out.println(" input clk;");
- System.out.println(" input data_Iscratch0_command_r;");
- System.out.println(" output data_Iscratch0_command_a;");
+ System.out.println(" input data_Memory0_command_r;");
+ System.out.println(" output data_Memory0_command_a;");
System.out.println(" output data_Debug0_out_r;");
System.out.println(" input data_Debug0_out_a;");
System.out.println(" output [(`PACKET_WIDTH-1):0] data_Debug0_out;");
- System.out.println(" input [(`PACKET_WIDTH-1):0] data_Iscratch0_command;");
- //System.out.println(" wire [(`INSTRUCTION_WIDTH-1):0] data_Iscratch0_ihorn;");
- //System.out.println(" wire [(`PACKET_WIDTH-1):0] data_Iscratch0_dhorn;");
+ System.out.println(" input [(`PACKET_WIDTH-1):0] data_Memory0_command;");
+ //System.out.println(" wire [(`INSTRUCTION_WIDTH-1):0] data_Memory0_ihorn;");
+ //System.out.println(" wire [(`PACKET_WIDTH-1):0] data_Memory0_dhorn;");
System.out.println();
System.out.println();
System.out.println("funnel topfun(clk,"+
" dest_r, dest_a, dest,"+
" source_r, source_a, source,"+
- " data_Iscratch0_dhorn_r, data_Iscratch0_dhorn_a, data_Iscratch0_dhorn);");
+ " data_Memory0_dhorn_r, data_Memory0_dhorn_a, data_Memory0_dhorn);");
*/
System.out.println("assign instruction_r = ihorn_r;");
System.out.println("assign ihorn_a = instruction_a;");
new SlipwayBenkoBox(false, this, "ihorn", true, true, false);
new SlipwayBenkoBox(false, this, "dhorn", true, false, true);
- } else if (type.equals("Iscratch")) {
- new SlipwayBenkoBox(true, this, "command", true);
+ } else if (type.equals("Memory")) {
+ new SlipwayBenkoBox(true, this, "command", true);
new SlipwayBenkoBox(false, this, "ihorn", true, true, false);
new SlipwayBenkoBox(false, this, "dhorn", true, false, true);
}
+++ /dev/null
-// output ///////////////////////////////////////////////////////////////////
-#expect 14
-#expect 13
-#expect 12
-#expect 11
-
-// program //////////////////////////////////////////////////////////////////
-#ship debug : Debug
-#ship dscratch : Dscratch
-#ship fifo : Fifo
-
-// dumb configurations
-debug.in: [*] take, deliver;
-dscratch.inWriteAddr: [*] take, deliver;
-dscratch.inWriteData: [*] take, deliver;
-dscratch.inReadAddr: [*] take, deliver;
-fifo.in: [*] take, deliver;
-
-// addresses and values to initialize the dscratch with
-1: sendto dscratch.inWriteAddr;
-2: sendto dscratch.inWriteAddr;
-3: sendto dscratch.inWriteAddr;
-4: sendto dscratch.inWriteAddr;
-11: sendto dscratch.inWriteData;
-12: sendto dscratch.inWriteData;
-13: sendto dscratch.inWriteData;
-14: sendto dscratch.inWriteData;
-
-// send write-completion tokens to the fifo output
-dscratch.outWriteDone:
- [*] take, sendto fifo.out;
-
-// when the write-completion tokens accumulate, unleash
-// the read addresses
-fifo.out:
- [4] wait;
- [4] take, sendto dscratch.inReadAddr;
-
-// read addresses
-4: sendto fifo.in;
-3: sendto fifo.in;
-2: sendto fifo.in;
-1: sendto fifo.in;
-
-// data read from dscratch goes to the debug ship
-dscratch.outReadData:
- [*] take, sendto debug.in;
-
projects / fleet.git / commitdiff