1 \documentclass[10pt,oneside]{book}
8 \renewcommand{\ttdefault}{cmtt}
9 \title{The FleetTwo Architecture Manual}
26 \section*{Programmer's View of The Ship-Fabric Interface}
28 The diagram below represents a {\it programmer's} conceptual view of
29 the interface between ships and the switch fabric. Actual
30 implementations may differ radically, as long as such differences are
31 not visible to software programs.
33 %\begin{wrapfigure}{R}{2in}
34 \epsfig{file=ports,width=6in}
37 The term {\it port} refers to each interface to the ship (either
38 inbound or outbound) and the machinery required to manage this
39 interface. The machinery consists of a {\it latch}, which is as wide
40 as a single machine word, a {\it pump}, which is a circular fifo of
41 instruction-width latches, and a number of {\it sources} or {\it
42 destinations}. Sources and destinations which can only send or
43 recieve tokens (rather than data items) are drawn as dashed lines.
44 Buffering fifos are drawn where they appear.
46 Note in particular that every pump is a destination capable of
47 recieving a data word. This is how instructions are dispatched to
48 pumps -- they are inserted into the switch fabric as {\it packets}
49 whose destination addresses
51 Note that addresses are actually paths.
58 \section*{Data Formats}
60 \subsection*{Packet Destination Address (12 bits)}
62 These bits appear physically within the switch fabric, and have
63 ``address bit timing.'' The {\tt T} bit is the ``tokenhood'' bit; if
64 set, this packet represents a token and it does not cause the switch
65 fabric data latches to fire.
69 \bitheader[b]{37,47,48}\\
71 \bitbox{11}{Destination Address}
76 \subsection*{Data Word In Memory (37 bits)}
78 A word of memory is 37 bits wide. For convenience, we assume that the
79 memory word width is also the width of a pointer as well as the width
80 of all on-chip data item registers.
86 \bitbox{37}{Data Word}
90 \subsection*{Data Packet In Flight (49 bits)}
92 A {\it data packet} is a data item in the switch fabric, on its way to
97 \bitheader[b]{0,36,37,47,48}\\
99 \bitbox{11}{Destination Address}
100 \bitbox{37}{Data Word}
104 \subsection*{Instruction In Memory (37 bits)}
106 An instruction must be no wider than a memory word. The next section
107 explains the bits in greater detail.
110 \begin{bytefield}{49}
111 \bitheader[b]{0,10,11,17,18-26,36}\\
113 \bitbox{11}{Instruction Register Address}
123 \bitbox{11}{Data/Token Destination}
127 \subsection*{Instruction Packet In Flight (49 bits)}
129 A {\it instruction packet} is an instruction in the instruction horn
130 (which may or may not be the same thing as the data horn), on its way
131 to some instruction register (Valve).
134 \begin{bytefield}{49}
135 \bitheader[b]{0,10,11,17,18-25,37,47,48}\\
137 \bitbox{11}{Instruction Register Address}
148 \bitbox{11}{Data/Token Destination}
155 \section*{Instruction Formats}
157 Instructions can be grouped into two categories: {\it killing}
158 instructions, which are acted upon as soon as they leave the
159 instruction horn, and {\it executing} instructions, which pass through
160 the instruction queue before being acted upon.
162 Blank fields below are reserved for future use and must be set to
165 Note that the arbiter is requested whenever {\it any of the first
166 three bits is {\tt 1}}. If the arbiter is not requested,
170 \setlength{\bitwidth}{5mm}
172 \subsection*{Killing Instructions}
174 Kill (kill anything other than a Clog)
177 \begin{bytefield}{26}
178 \bitheader[b]{0,6,7,20-25}\\
191 \begin{bytefield}{26}
192 \bitheader[b]{0,20-25}\\
201 \subsection*{Executing Instructions}
205 \begin{bytefield}{26}
206 \bitheader[b]{0,20-25}\\
215 Literal (sign extended, implicit {\tt Rq=1})
218 \begin{bytefield}{26}
219 \bitheader[b]{0,6,7,23-25}\\
230 \begin{bytefield}{26}
231 \bitheader[b]{0,6,7,17-25}\\
248 \subsection*{Field Descriptions}
250 \begin{bytefield}{26}
251 \bitheader[b]{0,6,7,16-25}\\
267 \item [\tt Ti] ({\bf Token Input}) wait for a token and accept
268 it\footnote{{\tt Ti}=1,{\tt Di}=1 is invalid on inbox.}
270 \item [\tt Di] ({\bf Data Input}) wait for a datum and accept it.
272 \item [\tt Dc] ({\bf Data Capture}) capture (latch) the accepted
273 datum. This bit is ignored if the incoming packet is
274 a token. \footnote{ Note that {\tt Di}=0,{\tt Dc}=1
275 is meaningless and therefore reserved for other
278 \item [\tt Do] ({\bf Data Output}) emit a datum.
280 \item [\tt To] ({\bf Token Output}) emit a token.\footnote{ {\tt To}=1,{\tt
281 Do}=1 have special meaning on an outbox.}
283 \item [\tt Ig] ({\bf Ignore {\tt To} Until Last Iteration}) ignore
284 the {\tt To} bit unless {\tt Count=0} \footnote{{\tt
285 To}=0,{\tt Ig}=1 is invalid}
287 \item [\tt Rq] ({\bf ReQueue}) if set, instructions having nonzero
288 count are ``Re-Queued'' rather than RePeated. See
289 {\tt Count} for more detail. \footnote{ An
290 instruction {\it in memory} may not have {\tt
291 Rq=1,Count=0} (use {\tt Rq=0,Count=0})}
293 \item [\tt Count] ({\bf Count}) {\it After} executing:
296 discard this instruction
298 if Count < MAX_COUNT {
302 put this instruction back into the instruction fifo
304 execute this instruction again
308 Note how a ``standing'' instruction is encoded as {\tt Count=1111111}
310 \item [\tt Dest] ({\bf Data/Token Destination})
311 Normally, this field is copied into the address portion of any
312 outgoing packet ({\tt Do} on an outbox or {\tt To}).
314 However, in the special case of an outbox, if {\tt Do=1,To=1}, then
315 the {\it most significant} {\tt 11} bits of the value in the {\it
316 data register} are used as a destination address instead. \footnote{This
317 functionality eliminates the need for any sort of ``{\tt Execute}''
318 ship, and lets a {\tt Fifo} ship act as an extension of the
319 instruction queue in the pump.}
324 \section{Future Directions}
326 Looking back on the design of the pump, several things are now
327 apparent which were not initially. In particular, it seems that it
328 could be useful to separate {\it loading the count register} from
329 other types of instructions. This would have a few advantages:
332 \item The size of the count field would not be a consideration in the
333 ``instruction budget'' of normal execution instructions
334 \item It would be possible to have finitely-repeating,
335 infinitely-requeueing instructions (FIXME).
345 dl (data literal, take from instruction bits)
348 doi (data output, destination taken from instruction)
349 dod (data output, destination taken from Data register)
355 requeue unconditionally
357 repeat unconditionally