3 (sys_clk_pin, /* I think this is 100Mhz */
5 fpga_0_RS232_Uart_1_ctsN_pin,
6 fpga_0_RS232_Uart_1_rtsN_pin,
7 fpga_0_RS232_Uart_1_sin_pin,
8 fpga_0_RS232_Uart_1_sout_pin
13 input fpga_0_RS232_Uart_1_ctsN_pin;
14 output fpga_0_RS232_Uart_1_rtsN_pin;
15 input fpga_0_RS232_Uart_1_sin_pin;
16 output fpga_0_RS232_Uart_1_sout_pin;
19 assign clk = sys_clk_pin;
23 reg send_k; initial send_k = 0;
25 assign rst = sys_rst_pin;
27 wire data_to_host_full;
28 wire data_to_host_write_enable;
29 wire [7:0] data_to_host;
31 wire data_to_fleet_empty;
32 wire data_to_fleet_read_enable;
33 wire [7:0] data_to_fleet;
37 reg [7:0] data_to_host_r;
38 assign data_to_host = data_to_host_r;
42 initial ser_rst_r = 0;
43 assign ser_rst = (rst & ser_rst_r);
47 sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
48 sasc_top sasc_top(clk, ser_rst,
49 fpga_0_RS232_Uart_1_sin_pin,
50 fpga_0_RS232_Uart_1_sout_pin,
51 fpga_0_RS232_Uart_1_ctsN_pin,
52 fpga_0_RS232_Uart_1_rtsN_pin,
57 data_to_fleet_read_enable,
58 data_to_host_write_enable,
64 // break and break_o are _active high_
65 always @(posedge clk) break_last <= break_o;
66 assign break = break_o && !break_last;
67 assign break_done = !break_o && break_last;
69 reg data_to_host_write_enable_reg;
70 reg data_to_fleet_read_enable_reg;
74 reg [7:0] root_in_d_reg;
80 wire [7:0] root_out_d;
83 root my_root(clk, rst && !break,
84 root_in_r, root_in_a, root_in_d,
85 root_out_r, root_out_a, root_out_d);
87 fifo4 my_root(clk, rst,
88 root_in_r, root_in_a, root_in_d,
89 root_out_r, root_out_a, data_to_host);
91 assign root_out_a = root_out_a_reg;
92 assign root_in_r = root_in_r_reg;
93 assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
94 assign data_to_host_write_enable = data_to_host_write_enable_reg;
95 assign root_in_d = root_in_d_reg;
102 data_to_host_write_enable_reg <= 0;
104 end else if (break_done) begin
105 data_to_host_write_enable_reg <= 1;
106 data_to_host_r <= 111;
108 end else if (send_k) begin
109 data_to_host_write_enable_reg <= 1;
110 data_to_host_r <= 107;
114 end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
115 data_to_host_write_enable_reg <= 1;
116 data_to_host_r <= root_out_d;
118 end else if (root_out_a_reg && !root_out_r) begin
119 data_to_host_write_enable_reg <= 0;
122 data_to_host_write_enable_reg <= 0;
127 always @(posedge clk)
133 data_to_fleet_read_enable_reg <= 0;
136 if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
138 root_in_d_reg <= data_to_fleet;
139 data_to_fleet_read_enable_reg <= 1;
141 data_to_fleet_read_enable_reg <= 0;
153 data_to_fleet_read_enable_reg = 0;
154 data_to_host_write_enable_reg = 0;