Marina/MarinaTest.java: a few hacks to get the silicon working
[fleet.git] / Makefile
index 049eda5..b2b1bd9 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -17,12 +17,13 @@ ship_files = $(shell find ships -name \*.ship)
 fleet.jar: $(java_files) $(ship_files) src/edu/berkeley/fleet/assembler/fleet.g
        mkdir -p build/class/edu/berkeley/fleet/assembler/
        cp src/edu/berkeley/fleet/assembler/fleet.g build/class/edu/berkeley/fleet/assembler/
-       javac -classpath lib/RXTXcomm.jar:lib/edu.berkeley.sbp.jar -d build/class/ $(shell find src -name \*.java)
+       javac -classpath lib/com.sun.async.test.jar:lib/ibex.jar:lib/RXTXcomm.jar:lib/edu.berkeley.sbp.jar -d build/class/ $(shell find src -name \*.java)
        cd build/class/; jar xf ../../lib/edu.berkeley.sbp.jar
+       cd build/class/; jar xf ../../lib/ibex.jar
        for A in `find ships -name \*.ship`;\
          do java -cp fleet.jar:build/class edu.berkeley.fleet.Main expand $$A;\
          done
-       javac -classpath lib/RXTXcomm.jar:build/class${ps}lib/edu.berkeley.sbp.jar -d build/class/ `find build/java -name \*.java`
+       javac -classpath lib/com.sun.async.test.jar:lib/ibex.jar:lib/RXTXcomm.jar:build/class${ps}lib/edu.berkeley.sbp.jar -d build/class/ `find build/java -name \*.java`
        echo 'Main-Class: edu.berkeley.fleet.Main' > build/class/manifest
        jar cmf build/class/manifest $@ ships -C build/class .
 
@@ -41,9 +42,12 @@ remote_edk = /tools/xilinx/10.1/EDK
 #remote_ise = /tools/xilinx/ISE9.1i_lin
 #remote_edk = /tools/xilinx/EDK9.1i
 
-#remote_dir = /scratch/megacz/fleet/
 #remote_dir = /vol/hitz/home/megacz/fleet/
-remote_dir = /tmp/megacz/fleet/
+#remote_dir = /tmp/megacz/fleet/
+
+remote_dir = /scratch/megacz/fleet/
+#remote_ise = /scratch/megacz/xilinx/10.1/ISE
+#remote_edk = /scratch/megacz/xilinx/10.1/EDK
 
 #host = mm2.millennium.berkeley.edu
 #remote_ise = /scratch/megacz/xilinx/ise/
@@ -57,6 +61,7 @@ xilinx += PATH=$$PATH:$(remote_ise)/bin/lin:$(remote_edk)/bin/lin
 #xilinx += XST_VERSION=9.2i
 xilinx += XILINX=$(remote_ise)
 xilinx += XIL_XST_HIDEMESSAGES=hdl_and_low_levels
+xilinx += XIL_PAR_DESIGN_CHECK_VERBOSE=1
 xilinx += XILINX_EDK=$(remote_edk)
 
 xilinx_ise = $(xilinx) $(remote_ise)/bin/lin/
@@ -79,11 +84,12 @@ board = ml505   # ??
 #package = 7ff1704
 
 device = ${part}${package}-${speed_grade}
+rsync = rsync --exclude=chips/marina/images -zare ssh --progress --verbose
 
 upload: fleet.jar build/fpga/main.bit
        mkdir -p build
        chmod +x misc/program.sh
-       rsync -are ssh --progress --verbose ./ root@goliath:fleet/
+       ${rsync} ./ root@goliath:fleet/
 
 build/fpga/main.bit: $(java_files) $(ship_files)
        make fleet.jar
@@ -94,21 +100,28 @@ build/fpga/main.bit: $(java_files) $(ship_files)
          do java -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\
          done
        ssh ${host} 'mkdir -p ${remote_dir}'
-       rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
+       ${rsync} --delete ./ ${host}:${remote_dir}
        time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_ise} remote_ise=${remote_ise} remote_edk=${remote_edk}'
        scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/
+       scp ${host}:${remote_dir}/build/fpga/main.ace build/fpga/
 
 pcore = ${remote_edk}/hw/XilinxProcessorIPLib/pcores
-#effort = std
-effort = high
+intstyle = -intstyle xflow
+effort = std
+#effort = high
+opt_for = area
+#opt_for = speed
 synth:
        cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
        cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
-       cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/greg/* .
+       cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/ddr2/* .
+       cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/dvi/* .
+       cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/zbt/* .
        rm -f build/fpga/main.lso
        echo work                        >> build/fpga/main.lso
        rm -f build/fpga/main.prj
        cd build/fpga; for A in *.v;   do echo verilog work \""$$A"\"; done >> main.prj
+       cd build/fpga; for A in *.vhd; do echo vhdl    work \""$$A"\"; done >> main.prj
        cd build/fpga; touch main.ini
        cd build/fpga; mkdir -p tmp
        cd build/fpga; mkdir -p xst
@@ -126,7 +139,7 @@ synth:
        echo -n " -ofmt NGC" >> build/fpga/main.xst
        echo -n " -p ${device}" >> build/fpga/main.xst
        echo -n " -top main" >> build/fpga/main.xst
-       echo -n " -opt_mode area" >> build/fpga/main.xst
+       echo -n " -opt_mode ${opt_for}" >> build/fpga/main.xst
        echo -n " -opt_level 2" >> build/fpga/main.xst
        echo -n " -iuc NO" >> build/fpga/main.xst
        echo -n " -lso main.lso" >> build/fpga/main.xst
@@ -196,21 +209,29 @@ synth:
        echo '-g Security:NONE' >> build/fpga/main.ut
        echo '-g Persist:No' >> build/fpga/main.ut
 
-       $(xilinx_ise)xst      -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
-       $(xilinx_ise)ngdbuild -intstyle xflow -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
-       $(xilinx_ise)map      -intstyle xflow -ol ${effort} -p $(device) -pr b -cm area -o main_map.ncd main.ngd main.pcf
-       $(xilinx_ise)par      -intstyle xflow -ol ${effort} -w main_map.ncd main.ncd main.pcf
-       $(xilinx_ise)bitgen   -intstyle xflow -f main.ut main.ncd
-#      $(xilinx_ise)trce     -intstyle xflow -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
-#      $(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
-#      mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
+       $(xilinx_ise)xst      ${intstyle} -ifn main.xst -ofn main.syr < main.xst \
+         | grep --line-buffered -v 'been backward balanced into' \
+         | grep --line-buffered -v 'IDDR has been replaced by IDDR_2CLK' \
+         | grep --line-buffered -v 'WARNING:Xst:616 - Invalid property'
+       cat build/fpga/*.ucf > build/fpga/main.ucf
+       $(xilinx_ise)ngdbuild ${intstyle} -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
+       $(xilinx_ise)map      ${intstyle} -ol ${effort} -p $(device) -pr b -cm ${opt_for} -o main_map.ncd main.ngd main.pcf
+       $(xilinx_ise)par      ${intstyle} -pl ${effort} -ol ${effort} -w main_map.ncd main.ncd main.pcf
+       $(xilinx_ise)trce     ${intstyle} -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
+       $(xilinx_ise)bitgen   ${intstyle} -f main.ut main.ncd
+       $(xilinx) tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
+       mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
 
 
 runserver: fleet.jar
        java -Djava.library.path=lib -cp fleet.jar:lib/RXTXcomm.jar edu.berkeley.fleet.fpga.Server
 
-test:     fleet.jar; $(java) -jar fleet.jar             test ships/*.ship tests
-testfpga: fleet.jar; $(java) -jar fleet.jar target=fpga test ships/*.ship tests
+test:     fleet.jar
+       $(java) -jar fleet.jar             test ships/*.ship tests
+       java -cp fleet.jar edu.berkeley.fleet.dataflow.MergeSort interpreter Memory 0 256
+testfpga: fleet.jar
+       $(java) -jar fleet.jar target=fpga test ships/*.ship tests
+       java -cp fleet.jar edu.berkeley.fleet.dataflow.MergeSort fpga Memory 0 256
 
 ## Manual ####################################################################################
 
@@ -270,6 +291,10 @@ javadoc:
 
 clean:
        rm -rf fleet.jar build
+       rm -f \
+         chips/marina/testCode/marina.xml \
+         chips/marina/testCode/marina.v \
+         chips/marina/testCode/marina.schematic-parasitics.spi
 
 ## Dist ####################################################################################
 
@@ -295,7 +320,6 @@ dist: fleet.jar
        darcs dist -d fleet
        mv fleet.tar.gz /afs/research.cs.berkeley.edu/class/fleet/website/code/snapshots/fleet-`date +%Y.%m.%d`.tgz
        mkdir -p .build
-       rm -f lib/suncvs.jar
        cd .build; for A in ../fleet.jar ../lib/*.jar; do jar xvf $$A; done
        cd .build; jar cvf /afs/research.cs.berkeley.edu/class/fleet/website/code/snapshots/fleet-`date +%Y.%m.%d`.jar .
        rm -rf .build
@@ -322,38 +346,84 @@ f0: fleet.jar
 
 ## Targets below are for integration with Sun-Proprietary Marina Test Chip ##############################
 
-cleansuncvs:
-       rm -rf lib/suncvs.jar suncvs
+electric_jar = ~/proj/electric/srcj/electric.jar
+electric = java -Xss2m -XX:MaxPermSize=128m -Xmx2000m -jar ${electric_jar}
+electric_headless = java -Xmx1500m -jar -Djava.awt.headless=true ${electric_jar} -batch
+all_electric_files = $(shell find chips/marina/electric/ -name \*.jelib -or -path \*.delib\*)
+modname = fakeMarinaPadframe
 
-lib/suncvs.jar: fleet.jar suncvs/marina suncvs/test
-       rm -rf suncvs/test/manuals
-       mkdir -p suncvs/build
-       cd suncvs; javac -cp ../fleet.jar:test/javamake.jar:test/jcommon.jar:test/jfreechart.jar -d build `find . -name \*.java`
-       cd suncvs/build; jar cvf ../../lib/suncvs.jar .
-       cd suncvs/test; jar uvf ../../lib/suncvs.jar .
+sun_server = simmons-tunnel
 
-sun_server = frehley
+#sun_server = frehley  # electric team uses frehley
 #sun_server = simmons
-
-runtest: fleet.jar
-       rm lib/suncvs.jar; make lib/suncvs.jar
-       rm -f suncvs/marina/testSims/isolatedInDock.spi.run
-       ssh ${sun_server} 'skill nanosim'
-       rsync -are ssh --delete --progress --verbose ./ ${sun_server}:~/fleet/
-       ssh ${sun_server} 'export PATH=$$PATH:/proj/async/cad/linux/bin/; cd ~/fleet/suncvs/marina/testSims; ln -s ../testCode/marina.xml ../testCode/marina.spi ../testCode/cfg .; /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java  -cp $$HOME/fleet/fleet.jar:$$HOME/fleet/lib/suncvs.jar com.sun.vlsi.chips.marina.test.MarinaTest -testNum 3021'
+#sun_server = criss    # criss is used for nohupped nanosim
+#sun_server = stanley  # stanley is used for nohupped hsim
+
+testnum = 0
+
+runtest: fleet.jar chips/marina/testCode/marina.xml chips/marina/testCode/marina.v chips/marina/testCode/marina.schematic-parasitics.spi
+       ${rsync} --delete ./ ${sun_server}:~/fleet/
+       time ssh -t -Y ${sun_server} 'cd ~/fleet/; make testlocal'
+
+silicon: fleet.jar chips/marina/testCode/marina.xml
+       ${rsync} --delete ./ ${sun_server}:~/fleet/
+       time ssh -t -Y ${sun_server} 'cd ~/fleet/; make siliconlocal'
+
+spice: fleet.jar
+       cp ~/omegaCounter.spi chips/marina/testCode/omegaCounter.spi
+       cp ~/omegaCounter-extracted.spi chips/marina/testCode/omegaCounter-extracted.spi
+       rsync -azre ssh --delete --progress --verbose ./ ${sun_server}:~/fleet/
+       ssh -t -Y ${sun_server} 'cd ~/fleet/chips/marina/testCode/; export PATH=/proj/async/cad/linux/bin/:$$PATH; echo -e "rcf commands\n" | hsim64 -time 90000 go.spi -o go.spi'
+
+
+testlocal: fleet.jar
+       cd chips/marina/testCode; \
+         export PATH=/proj/async/cad/linux/bin/:$$PATH; \
+         /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java \
+         -cp `pwd`/../../../lib/com.sun.async.test.jar:`pwd`/../../../fleet.jar \
+         com.sun.vlsi.chips.marina.test.MarinaTest \
+         -hsim \
+         -testNum ${testnum} || tail -n 20 marina.spi.run
+
+siliconlocal: fleet.jar
+       cd chips/marina/testCode; \
+         export PATH=/proj/async/cad/linux/bin/:$$PATH; \
+         /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java \
+         -cp `pwd`/../../../lib/com.sun.async.test.jar:`pwd`/../../../fleet.jar \
+         -Djava.library.path=/proj/async/cad/test/ \
+         com.sun.vlsi.chips.marina.test.MarinaTest \
+         -silicon \
+         -testNum ${testnum}
+
+chips/marina/testCode/marina.xml \
+chips/marina/testCode/marina.v \
+chips/marina/testCode/marina.schematic-parasitics.spi: ${all_electric_files}
+       @echo
+       @echo == Rebuilding Netlists and XML ===========================================================
+       rm -f chips/marina/testCode/marina.v
+       rm -f chips/marina/testCode/marina.schematic-parasitics.spi
+       rm -f chips/marina/testCode/marina.xml
+       cd chips/marina/testCode; \
+         nice -n 19 ${electric_headless} -s regen.bsh ../electric/aMarinaM.jelib
 
 electric:
-       rsync -are ssh --progress --verbose ${sun_server}:fleet/suncvs/marina/testSims/marina.spi.out ~/marina.spi.out
-       java -Xmx900m -jar /Applications/electric.jar suncvs/marina/electric/marinaL.jelib
-
-suncvs/test:
-       mkdir -p suncvs
-       cd suncvs; cvs -d ${sun_server}:/import/async/cad/cvs co test
-
-suncvs/marina:
-       mkdir -p suncvs
-       cd suncvs; cvs -d ${sun_server}:/import/async/cad/cvs co marina
-
+       ${electric} chips/marina/electric/aMarinaM.jelib
+
+chaing:
+       java -cp lib/com.sun.async.test.jar com.sun.async.test.ChainG chips/marina/testCode/marina.xml
+
+sync:
+       ${rsync} ${sun_server}:fleet/chips/marina/testCode/marina\*.dump ~/ || true
+       ${rsync} ${sun_server}:fleet/chips/marina/testCode/marina.spi.out ~/${modname}.out || true
+copyin:
+       cp ~/${modname}.spi chips/marina/testCode/marina.schematic-parasitics.spi || true
+       cp ~/${modname}.v   chips/marina/testCode/marina.v || true
+
+chips/marina/testCode/omegaCounter-extracted.spi: ${all_electric_files} chips/marina/testCode/rcx.bsh
+       @echo
+       @echo == Extracting Layout ===========================================================
+       ssh ${sun_server} 'rm -rf /tmp/am77536; mkdir /tmp/am77536'
+       cd chips/marina/testCode; \
+         nice -n 19 ${electric_headless} -s rcx.bsh ../electric/omegaCounter.jelib
+       mv chips/marina/electric/starrcxt/omegaCounter.sp $@
 
-syncspi:
-       rsync -are ssh --progress --verbose frehley:fleet/suncvs/marina/testSims/marina.spi.out ~/marina.spi.out