## Fleeterpreter ##############################################################################
ifeq ($(impl),ml509)
-java = java -Xmx500m -Dfleet.impl=edu.berkeley.fleet.fpga.Fpga
+java = java -Xmx500m -Dfleet.impl='edu.berkeley.fleet.fpga.ML509$$Large'
+effort = high
+opt_for = area
+xil_ver=10.1
+remote_ise = /tools/xilinx/${xil_ver}/ISE
+remote_edk = /tools/xilinx/${xil_ver}/EDK
+speed_grade = 1
+part = xc5vlx110t
+package = ff1136
+board = ml505 # ??
+runhost=goliath
+else
+ifeq ($(impl),bee2)
+java = java -Xmx500m -Dfleet.impl=edu.berkeley.fleet.fpga.Bee2
+# BEE2 does not work with ISE 10.1
+xil_ver=9.1i
+remote_ise = /tools/xilinx/ISE${xil_ver}_lin/
+remote_edk = /tools/xilinx/EDK${xil_ver}/
+effort = high
+opt_for = area
+part = xc2vp70
+package = ff1704
+speed_grade=6
+runhost=bee2-tunnel
else
ifeq ($(impl),java)
java = java -Xmx500m -Dfleet.impl=edu.berkeley.fleet.interpreter.Interpreter
else
+ifeq ($(impl),small)
+java = java -Xmx500m -Dfleet.impl='edu.berkeley.fleet.fpga.ML509$$Small'
+effort = std
+opt_for = area
+xil_ver=10.1
+remote_ise = /tools/xilinx/${xil_ver}/ISE
+remote_edk = /tools/xilinx/${xil_ver}/EDK
+speed_grade = 1
+part = xc5vlx110t
+package = ff1136
+board = ml505 # ??
+runhost=goliath
+else
java = java -Xmx500m
endif
endif
+endif
+endif
cp = -cp fleet.jar:lib/RXTXcomm.jar
cd build/class/; jar xf ../../lib/edu.berkeley.sbp.jar
cd build/class/; jar xf ../../lib/ibex.jar
for A in `find ships -name \*.ship`;\
- do $(java) -cp fleet.jar:build/class edu.berkeley.fleet.Main expand $$A;\
+ do java \
+ -cp fleet.jar:build/class \
+ -Dfleet.impl=edu.berkeley.fleet.interpreter.Interpreter \
+ edu.berkeley.fleet.Main \
+ expand $$A;\
done
javac -classpath lib/com.sun.async.test.jar:lib/ibex.jar:lib/RXTXcomm.jar:build/class${ps}lib/edu.berkeley.sbp.jar -d build/class/ `find build/java -name \*.java`
echo 'Main-Class: edu.berkeley.fleet.Main' > build/class/manifest
# 128Gb ram, 2x4-core. small-config:1189s large-config:3065s
#host = amdr905-1.eecs.berkeley.edu
-remote_ise = /tools/xilinx/10.1/ISE
-remote_edk = /tools/xilinx/10.1/EDK
-
-#remote_ise = /tools/xilinx/ISE9.1i_lin
-#remote_edk = /tools/xilinx/EDK9.1i
-
-#remote_dir = /vol/hitz/home/megacz/fleet/
-#remote_dir = /tmp/megacz/fleet/
-
remote_dir = /scratch/megacz/fleet/
-#remote_ise = /scratch/megacz/xilinx/10.1/ISE
-#remote_edk = /scratch/megacz/xilinx/10.1/EDK
+
#host = mm2.millennium.berkeley.edu
#remote_ise = /scratch/megacz/xilinx/ise/
xilinx_ise = $(xilinx) $(remote_ise)/bin/lin/
xilinx_edk = $(xilinx) $(remote_edk)/bin/lin/
-# ML50X
-speed_grade = 1
-part = xc5vlx110t
-package = ff1136
-board = ml505 # ??
-
# ML410
#part = xc4vfx60
#package = ff1152
#speed_grade = 11
#board = ml410
+#runhost=goliath
-# BEE2
-#part = xc2vp70
-#package = 7ff1704
-
-device = ${part}${package}-${speed_grade}
-rsync = rsync --exclude=chips/marina/images -zare ssh --progress --verbose
+device = ${part}-${package}-${speed_grade}
+rsync = rsync --exclude=.git --exclude=chips/marina/images -zare ssh --progress --verbose
upload: fleet.jar build/fpga/main.bit
mkdir -p build
chmod +x misc/program.sh
- ${rsync} ./ root@goliath:fleet/
+ ${rsync} fleet.jar build/fpga/main.bit misc root@${runhost}:fleet/
build/fpga/main.bit: $(java_files) $(ship_files)
- make fleet.jar
+ make fleet.jar impl=${impl}
mkdir -p build/fpga
$(java) $(cp) edu.berkeley.fleet.fpga.Fpga build/fpga/
cp src/edu/berkeley/fleet/fpga/* build/fpga || true
done
ssh ${host} 'mkdir -p ${remote_dir}'
${rsync} --delete ./ ${host}:${remote_dir}
- time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_ise} remote_ise=${remote_ise} remote_edk=${remote_edk}'
+ time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_ise} remote_ise=${remote_ise} remote_edk=${remote_edk} impl=${impl}'
scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/
- scp ${host}:${remote_dir}/build/fpga/main.ace build/fpga/
+ scp ${host}:${remote_dir}/build/fpga/main.ace build/fpga/ || true
pcore = ${remote_edk}/hw/XilinxProcessorIPLib/pcores
intstyle = -intstyle xflow
-effort = std
-#effort = high
-opt_for = area
-#opt_for = speed
synth:
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/ddr2/* .
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/dvi/* .
cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/zbt/* .
+ cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/bee2/* .
rm -f build/fpga/main.lso
echo work >> build/fpga/main.lso
rm -f build/fpga/main.prj
echo >> build/fpga/main.xst
rm -f build/fpga/main.ut
+ifneq ($(impl),bee2)
echo '-w' >> build/fpga/main.ut
echo '-g CclkPin:PULLUP' >> build/fpga/main.ut
echo '-g TdoPin:PULLNONE' >> build/fpga/main.ut
echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
echo '-g Security:NONE' >> build/fpga/main.ut
echo '-g Persist:No' >> build/fpga/main.ut
-
+endif
+ifeq ($(impl),bee2)
+ echo '-w' >> build/fpga/main.ut
+ echo '-g DebugBitstream:No' >> build/fpga/main.ut
+ echo '-g Binary:no' >> build/fpga/main.ut
+ echo '-g CRC:Enable' >> build/fpga/main.ut
+ echo '-g ConfigRate:4' >> build/fpga/main.ut
+ echo '-g CclkPin:PullUp' >> build/fpga/main.ut
+ echo '-g M0Pin:PullUp' >> build/fpga/main.ut
+ echo '-g M1Pin:PullUp' >> build/fpga/main.ut
+ echo '-g M2Pin:PullUp' >> build/fpga/main.ut
+ echo '-g ProgPin:PullUp' >> build/fpga/main.ut
+ echo '-g DonePin:PullUp' >> build/fpga/main.ut
+ echo '-g PowerdownPin:PullUp' >> build/fpga/main.ut
+ echo '-g TckPin:PullUp' >> build/fpga/main.ut
+ echo '-g TdiPin:PullUp' >> build/fpga/main.ut
+ echo '-g TdoPin:PullNone' >> build/fpga/main.ut
+ echo '-g TmsPin:PullUp' >> build/fpga/main.ut
+ echo '-g UnusedPin:PullDown' >> build/fpga/main.ut
+ echo '-g UserID:0xFFFFFFFF' >> build/fpga/main.ut
+ echo '-g DCMShutdown:Disable' >> build/fpga/main.ut
+ echo '-g DisableBandgap:No' >> build/fpga/main.ut
+ echo '-g DCIUpdateMode:AsRequired' >> build/fpga/main.ut
+ echo '-g StartUpClk:CClk' >> build/fpga/main.ut
+ echo '-g DONE_cycle:4' >> build/fpga/main.ut
+ echo '-g GTS_cycle:5' >> build/fpga/main.ut
+ echo '-g GWE_cycle:6' >> build/fpga/main.ut
+ echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
+ echo '-g Security:None' >> build/fpga/main.ut
+ echo '-g DonePipe:No' >> build/fpga/main.ut
+ echo '-g DriveDone:No' >> build/fpga/main.ut
+ echo '-g Encrypt:No' >> build/fpga/main.ut
+endif
$(xilinx_ise)xst ${intstyle} -ifn main.xst -ofn main.syr < main.xst \
| grep --line-buffered -v 'been backward balanced into' \
| grep --line-buffered -v 'IDDR has been replaced by IDDR_2CLK' \
$(xilinx_ise)par ${intstyle} -pl ${effort} -ol ${effort} -w main_map.ncd main.ncd main.pcf
$(xilinx_ise)trce ${intstyle} -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
$(xilinx_ise)bitgen ${intstyle} -f main.ut main.ncd
+ifneq ($(impl),bee2)
$(xilinx) tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
mv build/fpga/mainx.ace build/fpga/main.ace # genace throws a fit if the filename prefix is the same?
-
+endif
runserver: fleet.jar
$(java) -Djava.library.path=lib -cp fleet.jar:lib/RXTXcomm.jar edu.berkeley.fleet.fpga.Server
$(java) -jar fleet.jar test ships/*.ship tests
$(java) -cp fleet.jar edu.berkeley.fleet.dataflow.MergeSort Memory 0 256
+demo: fleet.jar
+ $(java) -cp fleet.jar edu.berkeley.fleet.dataflow.SortingDemo
+
## Manual ####################################################################################
svgs = $(shell find doc -name \*.svg)
runtest: fleet.jar chips/marina/testCode/marina.xml chips/marina/testCode/marina.v chips/marina/testCode/marina.schematic-parasitics.spi
${rsync} --delete ./ ${sun_server}:~/fleet/
- time ssh -t -Y ${sun_server} 'cd ~/fleet/; make testlocal'
+ time ssh -t -Y ${sun_server} 'cd ~/fleet/; make testlocal impl=${impl}'
silicon: fleet.jar chips/marina/testCode/marina.xml
${rsync} --delete ./ ${sun_server}:~/fleet/
- time ssh -t -Y ${sun_server} 'cd ~/fleet/; make siliconlocal'
+ time ssh -t -Y ${sun_server} 'cd ~/fleet/; make siliconlocal impl=${impl}'
spice: fleet.jar
cp ~/omegaCounter.spi chips/marina/testCode/omegaCounter.spi
projects / fleet.git / blobdiff