Bee2 branch landing: step 1

[fleet.git] / Makefile

diff --git a/Makefile b/Makefile
index e2f407b..cf1f3eb 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -6,13 +6,26 @@ java              = java -Xmx500m -Dfleet.impl='edu.berkeley.fleet.fpga.ML509$$L
 effort = high
 opt_for = area
 xil_ver=10.1
+remote_ise = /tools/xilinx/${xil_ver}/ISE
+remote_edk = /tools/xilinx/${xil_ver}/EDK
+speed_grade = 1
+part = xc5vlx110t
+package = ff1136
+board = ml505   # ??
+runhost=goliath
 else
 ifeq ($(impl),bee2)
 java              = java -Xmx500m -Dfleet.impl=edu.berkeley.fleet.fpga.Bee2
 # BEE2 does not work with ISE 10.1
 xil_ver=9.1i
+remote_ise = /tools/xilinx/ISE${xil_ver}_lin/
+remote_edk = /tools/xilinx/EDK${xil_ver}/
 effort = high
 opt_for = area
+part = xc2vp70
+package = ff1704
+speed_grade=6
+runhost=bee2-tunnel
 else
 ifeq ($(impl),java)
 java              = java -Xmx500m -Dfleet.impl=edu.berkeley.fleet.interpreter.Interpreter
@@ -22,6 +35,13 @@ java              = java -Xmx500m -Dfleet.impl='edu.berkeley.fleet.fpga.ML509$$S
 effort = std
 opt_for = area
 xil_ver=10.1
+remote_ise = /tools/xilinx/${xil_ver}/ISE
+remote_edk = /tools/xilinx/${xil_ver}/EDK
+speed_grade = 1
+part = xc5vlx110t
+package = ff1136
+board = ml505   # ??
+runhost=goliath
 else
 java              = java -Xmx500m
 endif
@@ -68,8 +88,6 @@ host = intel2950-5.eecs.berkeley.edu
 #host = amdr905-1.eecs.berkeley.edu
 
 remote_dir = /scratch/megacz/fleet/
-remote_ise = /tools/xilinx/${xil_ver}/ISE
-remote_edk = /tools/xilinx/${xil_ver}/EDK
 
 
 #host = mm2.millennium.berkeley.edu
@@ -90,29 +108,20 @@ xilinx += XILINX_EDK=$(remote_edk)
 xilinx_ise = $(xilinx) $(remote_ise)/bin/lin/
 xilinx_edk = $(xilinx) $(remote_edk)/bin/lin/
 
-# ML50X
-speed_grade = 1
-part = xc5vlx110t
-package = ff1136
-board = ml505   # ??
-
 # ML410
 #part = xc4vfx60
 #package = ff1152
 #speed_grade = 11
 #board = ml410
+#runhost=goliath
 
-# BEE2
-#part = xc2vp70
-#package = 7ff1704
-
-device = ${part}${package}-${speed_grade}
+device = ${part}-${package}-${speed_grade}
 rsync = rsync --exclude=.git --exclude=chips/marina/images -zare ssh --progress --verbose
 
 upload: fleet.jar build/fpga/main.bit
        mkdir -p build
        chmod +x misc/program.sh
-       ${rsync} ./ root@goliath:fleet/
+       ${rsync} fleet.jar build/fpga/main.bit misc root@${runhost}:fleet/
 
 build/fpga/main.bit: $(java_files) $(ship_files)
        make fleet.jar impl=${impl}
@@ -126,7 +135,7 @@ build/fpga/main.bit: $(java_files) $(ship_files)
        ${rsync} --delete ./ ${host}:${remote_dir}
        time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_ise} remote_ise=${remote_ise} remote_edk=${remote_edk} impl=${impl}'
        scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/
-       scp ${host}:${remote_dir}/build/fpga/main.ace build/fpga/
+       scp ${host}:${remote_dir}/build/fpga/main.ace build/fpga/ || true
 
 pcore = ${remote_edk}/hw/XilinxProcessorIPLib/pcores
 intstyle = -intstyle xflow
@@ -136,6 +145,7 @@ synth:
        cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/ddr2/* .
        cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/dvi/* .
        cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/zbt/* .
+       cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/bee2/* .
        rm -f build/fpga/main.lso
        echo work                        >> build/fpga/main.lso
        rm -f build/fpga/main.prj
@@ -207,6 +217,7 @@ synth:
        echo >> build/fpga/main.xst
 
        rm -f build/fpga/main.ut
+ifneq ($(impl),bee2)
        echo '-w' >> build/fpga/main.ut
        echo '-g CclkPin:PULLUP' >> build/fpga/main.ut
        echo '-g TdoPin:PULLNONE' >> build/fpga/main.ut
@@ -227,7 +238,39 @@ synth:
        echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
        echo '-g Security:NONE' >> build/fpga/main.ut
        echo '-g Persist:No' >> build/fpga/main.ut
-
+endif
+ifeq ($(impl),bee2)
+       echo '-w' >> build/fpga/main.ut
+       echo '-g DebugBitstream:No' >> build/fpga/main.ut
+       echo '-g Binary:no' >> build/fpga/main.ut
+       echo '-g CRC:Enable' >> build/fpga/main.ut
+       echo '-g ConfigRate:4' >> build/fpga/main.ut
+       echo '-g CclkPin:PullUp' >> build/fpga/main.ut
+       echo '-g M0Pin:PullUp' >> build/fpga/main.ut
+       echo '-g M1Pin:PullUp' >> build/fpga/main.ut
+       echo '-g M2Pin:PullUp' >> build/fpga/main.ut
+       echo '-g ProgPin:PullUp' >> build/fpga/main.ut
+       echo '-g DonePin:PullUp' >> build/fpga/main.ut
+       echo '-g PowerdownPin:PullUp' >> build/fpga/main.ut
+       echo '-g TckPin:PullUp' >> build/fpga/main.ut
+       echo '-g TdiPin:PullUp' >> build/fpga/main.ut
+       echo '-g TdoPin:PullNone' >> build/fpga/main.ut
+       echo '-g TmsPin:PullUp' >> build/fpga/main.ut
+       echo '-g UnusedPin:PullDown' >> build/fpga/main.ut
+       echo '-g UserID:0xFFFFFFFF' >> build/fpga/main.ut
+       echo '-g DCMShutdown:Disable' >> build/fpga/main.ut
+       echo '-g DisableBandgap:No' >> build/fpga/main.ut
+       echo '-g DCIUpdateMode:AsRequired' >> build/fpga/main.ut
+       echo '-g StartUpClk:CClk' >> build/fpga/main.ut
+       echo '-g DONE_cycle:4' >> build/fpga/main.ut
+       echo '-g GTS_cycle:5' >> build/fpga/main.ut
+       echo '-g GWE_cycle:6' >> build/fpga/main.ut
+       echo '-g LCK_cycle:NoWait' >> build/fpga/main.ut
+       echo '-g Security:None' >> build/fpga/main.ut
+       echo '-g DonePipe:No' >> build/fpga/main.ut
+       echo '-g DriveDone:No' >> build/fpga/main.ut
+       echo '-g Encrypt:No' >> build/fpga/main.ut
+endif
        $(xilinx_ise)xst      ${intstyle} -ifn main.xst -ofn main.syr < main.xst \
          | grep --line-buffered -v 'been backward balanced into' \
          | grep --line-buffered -v 'IDDR has been replaced by IDDR_2CLK' \
@@ -238,9 +281,10 @@ synth:
        $(xilinx_ise)par      ${intstyle} -pl ${effort} -ol ${effort} -w main_map.ncd main.ncd main.pcf
        $(xilinx_ise)trce     ${intstyle} -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
        $(xilinx_ise)bitgen   ${intstyle} -f main.ut main.ncd
+ifneq ($(impl),bee2)
        $(xilinx) tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
        mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
-
+endif
 
 runserver: fleet.jar
        $(java) -Djava.library.path=lib -cp fleet.jar:lib/RXTXcomm.jar edu.berkeley.fleet.fpga.Server