migrate jelib->delib

[fleet.git] / chips / marina / electric / centersJ.delib / ctrAND1in30.lay

diff --git a/chips/marina/electric/centersJ.delib/ctrAND1in30.lay b/chips/marina/electric/centersJ.delib/ctrAND1in30.lay
new file mode 100644 (file)
index 0000000..ea46af3
--- /dev/null
+++ b/chips/marina/electric/centersJ.delib/ctrAND1in30.lay
@@ -0,0 +1,36 @@
+HcentersJ|8.10k
+
+# External Libraries:
+
+Lgates1inM|gates1inM
+
+# Cell ctrAND1in30;1{lay}
+CctrAND1in30;1{lay}||cmos90|1231629883946|1241981698008||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1241981751253
+Ngeneric:Facet-Center|art@0||0|0||||AV
+Igates1inM:inv05;1{lay}|inv05@1||-20.5|0|X||D5G4;
+Igates1inM:inv10D;1{lay}|inv10D@1||-12|0|||D5G4;
+Igates1inM:inv30;1{lay}|inv30@1||13|0|||D5G4;
+NMetal-1-Pin|pin@0||-6|25||||
+NMetal-1-Pin|pin@1||-6|-25||||
+NMetal-1-Pin|pin@3||-25|-25||||
+Ametal-2|net@4|||RS0|inv05@1|gnd|-11.5|0|inv10D@1|gnd|-20.5|0
+Ametal-2|net@5|||RS0|inv05@1|vdd|-11.5|50|inv10D@1|vdd|-20.5|50
+Ametal-2|net@6|||RS0|inv05@1|vdd_1|-11.5|-50|inv10D@1|vdd_1|-20.5|-50
+Ametal-2|net@7|||S0|inv30@1|gnd|-3.5|0|inv10D@1|gnd_1|-3.5|0
+Ametal-2|net@8|||S0|inv30@1|vdd|-3.5|50|inv10D@1|vdd_2|-3.5|50
+Ametal-2|net@9|||S0|inv30@1|vdd_1|-3.5|-50|inv10D@1|vdd_3|-3.5|-50
+Ametal-1|net@10|||S0|inv30@1|inB|6|25|pin@0||-6|25
+Ametal-1|net@11|||S900|pin@0||-6|25|inv10D@1|out|-6|7
+Ametal-1|net@12|||S0|inv30@1|inA|6|-25|pin@1||-6|-25
+Ametal-1|net@13|||S2700|pin@1||-6|-25|inv10D@1|out|-6|7
+Ametal-1|net@15|||S0|inv10D@1|in|-12|-25|pin@3||-25|-25
+Ametal-1|net@16|||S2700|pin@3||-25|-25|inv05@1|out[1]|-25|-7
+Egnd_1|gnd|D5G2;|inv05@1|gnd_1|G
+Egnd_2||D5G2;|inv30@1|gnd_1|G
+Ein[1]|in|D5G2;|inv05@1|in[1]|I
+Eout||D5G2;|inv30@1|out|O
+Evdd_2|vdd|D5G2;|inv05@1|vdd_2|P
+Evdd_3||D5G2;|inv05@1|vdd_3|P
+Evdd_4||D5G2;|inv30@1|vdd_2|P
+Evdd_5||D5G2;|inv30@1|vdd_3|P
+X