migrate jelib->delib

[fleet.git] / chips / marina / electric / driversM.delib / latchAndDriver30.sch

diff --git a/chips/marina/electric/driversM.delib/latchAndDriver30.sch b/chips/marina/electric/driversM.delib/latchAndDriver30.sch
new file mode 100644 (file)
index 0000000..9bffb68
--- /dev/null
+++ b/chips/marina/electric/driversM.delib/latchAndDriver30.sch
@@ -0,0 +1,38 @@
+HdriversM|8.10k
+
+# External Libraries:
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LredFive|redFive
+
+# Cell latchAndDriver30;1{sch}
+ClatchAndDriver30;1{sch}||schematic|1194830486721|1235129233701|
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||18|0||||
+NOff-Page|conn@1||-18|-2||||
+NOff-Page|conn@2||-18|2||||
+IredFive:inv;1{ic}|inv@0||9|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IlatchAndDriver30;1{ic}|latchAnd@1||24.5|12.5|||D5G4;
+IredFive:nand2;1{ic}|nand2@0||-9|0|XYRR||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Ngeneric:Invisible-Pin|pin@0||0.5|27|||||ART_message(D5G6;)SlatchAndDriver30
+Ngeneric:Invisible-Pin|pin@1||-0.5|18|||||ART_message(D5G3;)Sies 14 November 2008
+Ngeneric:Invisible-Pin|pin@2||-1.5|22|||||ART_message(D5G4;)Sdriver for 37 data latches
+NWire_Pin|pin@5||-14|-2||||
+NWire_Pin|pin@6||-14|-1||||
+NWire_Pin|pin@7||-14|2||||
+NWire_Pin|pin@8||-14|1||||
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||0|0|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D387.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+Awire|net@8|||1800|wire90@0|b|2.5|0|inv@0|in|6.5|0
+Awire|net@9|||1800|inv@0|out|11.5|0|conn@0|a|16|0
+Awire|net@20|||1800|conn@1|y|-16|-2|pin@5||-14|-2
+Awire|net@21|||2700|pin@5||-14|-2|pin@6||-14|-1
+Awire|net@22|||1800|pin@6||-14|-1|nand2@0|ina|-11.5|-1
+Awire|net@23|||1800|conn@2|y|-16|2|pin@7||-14|2
+Awire|net@24|||900|pin@7||-14|2|pin@8||-14|1
+Awire|net@25|||1800|pin@8||-14|1|nand2@0|inb|-11.5|1
+Awire|net@26|||0|wire90@0|a|-2.5|0|nand2@0|out|-6.5|0
+EinA||D4G2;|conn@1|a|I
+EinB||D4G2;|conn@2|a|I
+Eout||D6G2;|conn@0|y|O
+X