migrate jelib->delib

[fleet.git] / chips / marina / electric / gates2inM.delib / nand60sym.sch

diff --git a/chips/marina/electric/gates2inM.delib/nand60sym.sch b/chips/marina/electric/gates2inM.delib/nand60sym.sch
new file mode 100644 (file)
index 0000000..6d68736
--- /dev/null
+++ b/chips/marina/electric/gates2inM.delib/nand60sym.sch
@@ -0,0 +1,23 @@
+Hgates2inM|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell nand60sym;1{sch}
+Cnand60sym;1{sch}||schematic|1189031371358|1205536772914|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||11|0||||
+NOff-Page|conn@1||-9.5|-1|||Y|
+NOff-Page|conn@2||-9.5|1|||Y|
+IredFive:nand2_sy;1{ic}|nor2n@0||-0.5|0|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S60|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Ngeneric:Invisible-Pin|pin@0||0|12.5|||||ART_message(D5G5;)Snand60sym
+Ngeneric:Invisible-Pin|pin@1||0.5|8.5|||||ART_message(D5G3;)Sies 25 October 2007
+Ngeneric:Invisible-Pin|pin@2||-8.5|-7|||||ART_message(D6G2;)S[of 941 wire length on out,"468 is in drains, 473 real"]
+Awire|net@0|||1800|conn@1|y|-7.5|-1|nor2n@0|ina|-3|-1
+Awire|net@1|||1800|conn@2|y|-7.5|1|nor2n@0|inb|-3|1
+Awire|net@2|||1800|nor2n@0|out|2|0|conn@0|a|9|0
+EinA||D4G2;|conn@1|a|I
+EinB||D4G2;|conn@2|a|I
+Eout||D6G2;|conn@0|y|O
+X