migrate jelib->delib

[fleet.git] / chips / marina / electric / orangeTSMC090nm.delib / PMOSf_io25.sch

diff --git a/chips/marina/electric/orangeTSMC090nm.delib/PMOSf_io25.sch b/chips/marina/electric/orangeTSMC090nm.delib/PMOSf_io25.sch
new file mode 100644 (file)
index 0000000..8edf558
--- /dev/null
+++ b/chips/marina/electric/orangeTSMC090nm.delib/PMOSf_io25.sch
@@ -0,0 +1,26 @@
+HorangeTSMC090nm|8.10k
+
+# Cell PMOSf_io25;1{sch}
+CPMOSf_io25;1{sch}||schematic|1021415734000|1159313441380||ATTR_Delay(D5G1;HNPX-8.5;Y-1.25;)I100|ATTR_L(D5FLeave alone;G1;HNOLPX-8.5;Y0.25;)S5.6|ATTR_W(D5FLeave alone;G1;HNOLPX-8.75;Y2;)S3|ATTR_CDL_template(D5G1;NTX2.5;Y-15.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_NCC(D5G1;NTX1;Y-13;)StransistorType  OD25-P-Transistor|ATTR_SPICE_template(D5G1;NTX3.5;Y-9;)SM$(node_name) $(d) $(g) $(s) vdd pch_25 W='$(W)*(1+ABP/sqrt($(W)*$(L)))' L='$(L)' DELVTO='AVT0P/sqrt($(W)*$(L))'|ATTR_SPICE_template_calibre(D5G1;NTX3;Y-17.5;)SM$(node_name) $(d) $(g) $(s) vdd pch_25 W='$(W)*0.05u' L='$(L)*0.05u'|ATTR_SPICE_template_smartspice(D5G1;NTX1;Y-7;)SM$(node_name) $(d) $(g) $(s) vdd pch_25 W='$(W)' L='$(L)'|ATTR_verilog_template(D5G1;NTX1;Y-11;)Stranif0 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+IPMOSf_io25;1{ic}|PMOS4f@0||23.25|11.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5FLeave alone;G1;NOLPX3.5;)S5.6|ATTR_W(D5FLeave alone;G1;NOLPX3;Y1;)S3
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||5|11.5||||
+NOff-Page|conn@2||-12|7||||
+NOff-Page|conn@3||5|1||||
+NWire_Pin|pin@0||0|11.5||||
+NWire_Pin|pin@1||0|1||||
+Ngeneric:Invisible-Pin|pin@2||-1|27|||||ART_message(D5G6;)SPMOSf_io25
+Ngeneric:Invisible-Pin|pin@3||-1.5|21.5|||||ART_message(D5G2;)S3-terminal PMOS device for 2.5V I/O pads
+Ngeneric:Invisible-Pin|pin@4||-1|17.5|||||ART_message(D5G2;)Sminimum length for 2.5V thick-oxide devices is 5.6
+N4-Port-Transistor|pmos4p@0||-2|7|||YR|2|ATTR_length(D5FLeave alone;G1;OLX1.5;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX-0.5;Y-2;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3.5;)Spch_25
+NPower|pwr@0||7|8||||
+Awire|net@0|||0|pmos4p@0|g|-3|7|conn@2|y|-10|7
+Awire|net@1|||1800|pin@0||0|11.5|conn@0|a|3|11.5
+Awire|net@2|||2700|pmos4p@0|s|0|9|pin@0||0|11.5
+Awire|net@4|||0|conn@3|a|3|1|pin@1||0|1
+Awire|net@5|||2700|pin@1||0|1|pmos4p@0|d|0|5
+Awire|net@6|||0|pwr@0||7|8|pmos4p@0|b|0|8
+Ed||D5G2;|conn@3|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X