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[fleet.git] / chips / marina / electric / orangeTSMC090nm.delib / gallery.sch
diff --git a/chips/marina/electric/orangeTSMC090nm.delib/gallery.sch b/chips/marina/electric/orangeTSMC090nm.delib/gallery.sch
new file mode 100644 (file)
index 0000000..40b668a
--- /dev/null
+++ b/chips/marina/electric/orangeTSMC090nm.delib/gallery.sch
@@ -0,0 +1,102 @@
+HorangeTSMC090nm|8.10k
+
+# Cell gallery;1{sch}
+Cgallery;1{sch}||schematic|1158082936168|1158346546100|
+INMOS4f;1{ic}|NMOS4f@0||-28|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_high;1{ic}|NMOS4f_h@0||-37|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_io18;1{ic}|NMOS4f_i@0||-45.5|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S4|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_io25;1{ic}|NMOS4f_i@1||-54.5|50.5|||D5G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S5.6|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_io33;1{ic}|NMOS4f_i@2||-63.5|50.5|||D5G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S7.6|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_low;1{ic}|NMOS4f_l@0||-19|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOS4f_native;1{ic}|NMOS4f_n@0||-10|50.5|||D5G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S4|ATTR_W(D6G1;NPX1.75;Y0.75;)S10
+INMOS4fwk;1{ic}|NMOS4fwk@0||11|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOS4fwk_low;1{ic}|NMOS4fwk@1||20|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOS4fwk_high;1{ic}|NMOS4fwk@2||2|50.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOS4fwk_native;1{ic}|NMOS4fwk@3||29|51|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D6G1;NPX2;Y1;)S10|ATTR_GEO()I0
+INMOS4x;1{ic}|NMOS4x@0||-28|74|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)S1
+INMOS4x_io25;1{ic}|NMOS4x_i@0||-54.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOS4x_io33;1{ic}|NMOS4x_i@1||-63|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOS4x_io18;1{ic}|NMOS4x_i@2||-45.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSf;1{ic}|NMOSf@0||-28|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_high;1{ic}|NMOSf_hi@0||-37|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_io25;1{ic}|NMOSf_io@0||-54.5|57.5|||D5G4;|ATTR_Delay(P)I100|ATTR_L(D5G1;NPX3.5;)S5.6|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_io33;1{ic}|NMOSf_io@1||-63.5|57.5|||D5G4;|ATTR_Delay(P)I100|ATTR_L(D5G1;NPX3.5;)S7.6|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_io18;1{ic}|NMOSf_io@2||-45.5|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.25;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)S4|ATTR_W(D6G1;NPX1.75;Y0.75;)I3
+INMOSf_low;1{ic}|NMOSf_lo@0||-19|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+INMOSf_native;1{ic}|NMOSf_na@0||-10|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D6G1;NPX2;Y1;)S10
+INMOSf_native_od25;1{ic}|NMOSf_na@1||-84.5|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S24|ATTR_W(D6G1;NPX2;Y1;)S10
+INMOSf_native_od18;1{ic}|NMOSf_na@2||-75.5|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S24|ATTR_W(D6G1;NPX2;Y1;)S10
+INMOSf_native_od33;1{ic}|NMOSf_na@3||-94.5|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S24|ATTR_W(D6G1;NPX2;Y1;)S10
+INMOSfwk;1{ic}|NMOSfwk@0||11|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOSfwk_low;1{ic}|NMOSfwk_@0||20|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOSfwk_high;1{ic}|NMOSfwk_@1||2|57.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+INMOSfwk_native;1{ic}|NMOSfwk_@2||29|57.5|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D6G1;NPX2;Y1;)S10|ATTR_GEO()I0
+INMOSx;1{ic}|NMOSx@0||-28|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSx_high;1{ic}|NMOSx_hi@0||-37|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSx_low;1{ic}|NMOSx_lo@0||-19|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSx_native;1{ic}|NMOSx_na@0||-10|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+INMOSx_native_od25;1{ic}|NMOSx_na@1||-84.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+INMOSx_native_od18;1{ic}|NMOSx_na@2||-75.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+INMOSx_native_od33;1{ic}|NMOSx_na@3||-94.5|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+INMOSxwk;1{ic}|NMOSxwk@0||11|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSxwk_low;1{ic}|NMOSxwk_@0||20|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSxwk_high;1{ic}|NMOSxwk_@1||2|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+INMOSxwk_native;1{ic}|NMOSxwk_@2||29|66|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOS4f;1{ic}|PMOS4f@0||-28|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4f_high;1{ic}|PMOS4f_h@0||-37|13|||D0G4;|ATTR_Delay(D5G1;NPX3.75;Y-2.25;)I100|ATTR_L(D5G1;NPX3.25;Y-0.25;)I2|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOS4f_io18;1{ic}|PMOS4f_i@0||-45.5|13|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOS4f_io25;1{ic}|PMOS4f_i@1||-54.5|13|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S5.6|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOS4f_io33;1{ic}|PMOS4f_i@2||-63.5|13|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S7.6|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOS4f_low;1{ic}|PMOS4f_l@0||-19|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4fwk;1{ic}|PMOS4fwk@0||11|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4fwk_high;1{ic}|PMOS4fwk@1||2|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4fwk_low;1{ic}|PMOS4fwk@2||20|13|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOS4x;1{ic}|PMOS4x@0||-28|35.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOS4x_io25;1{ic}|PMOS4x_i@0||-54.5|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_L()I2|ATTR_W()I3
+IPMOS4x_io33;1{ic}|PMOS4x_i@1||-63.5|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_L()I2|ATTR_W()I3
+IPMOS4x_io18;1{ic}|PMOS4x_i@2||-45.5|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1|ATTR_L()I2|ATTR_W()I3
+IPMOSf;1{ic}|PMOSf@0||-28|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOSf_high;1{ic}|PMOSf_hi@0||-37|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOSf_io18;1{ic}|PMOSf_io@0||-45.5|20|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S4|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOSf_io25;1{ic}|PMOSf_io@1||-54.5|20|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S5.6|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOSf_io33;1{ic}|PMOSf_io@2||-63.5|20|||D5G4;|ATTR_Delay(D5G1;NPX3.5;Y-2.5;)I100|ATTR_L(D5G1;NPX3.5;)S7.6|ATTR_W(D5G1;NPX3;Y1;)I3
+IPMOSf_low;1{ic}|PMOSf_lo@0||-18.75|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3
+IPMOSfwk;1{ic}|PMOSfwk@0||11|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+IPMOSfwk_high;1{ic}|PMOSfwk_@0||2|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+IPMOSfwk_low;1{ic}|PMOSfwk_@1||20|20|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_L(D5G1;NPX3.5;)I2|ATTR_W(D6G1;NPX2;Y1;)I3|ATTR_GEO()I0
+IPMOSx;1{ic}|PMOSx@0||-28|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSx_high;1{ic}|PMOSx_hi@0||-37|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSx_low;1{ic}|PMOSx_lo@0||-19|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSxwk;1{ic}|PMOSxwk@0||11|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSxwk_high;1{ic}|PMOSxwk_@0||2|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IPMOSxwk_low;1{ic}|PMOSxwk_@1||20|27.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)I1
+IR110;1{ic}|R110@0||-95|17|||D5G1;T|ATTR_L(D5G1;NPX-2;Y-2.25;)I40|ATTR_W(D5G1;NPX2.25;Y-2.25;)D8.8
+IR440;1{ic}|R440@0||-95|10.5|||D5G1;T|ATTR_L(D5G1;NPX-2;Y-2.25;)I40|ATTR_W(D5G1;NPX2.25;Y-2.25;)D8.8
+Ngeneric:Facet-Center|art@0||0|0||||AV
+IgateResistor;1{ic}|gateResi@0||-95.5|40.5|||D0G4;|ATTR_W(D5G1;NPY-1.5;)I3
+Indio;1{ic}|ndio@0||-79|36|||D5G4;
+Ngeneric:Invisible-Pin|pin@1||-38|86|||||ART_message(D5G2;R)Shigh-threshold
+Ngeneric:Invisible-Pin|pin@2||-19.5|86|||||ART_message(D5G2;R)Slow-threshold
+Ngeneric:Invisible-Pin|pin@3||-10.5|86|||||ART_message(D5G2;R)Snative
+Ngeneric:Invisible-Pin|pin@4||-28.5|86|||||ART_message(D5G2;R)Sstandard
+Ngeneric:Invisible-Pin|pin@5||-46|86|||||ART_message(D5G2;R)S1.8V thick-ox
+Ngeneric:Invisible-Pin|pin@6||-55|86|||||ART_message(D5G2;R)S2.5V thick-ox
+Ngeneric:Invisible-Pin|pin@7||-64|86|||||ART_message(D5G2;R)S3.3V thick-ox
+Ngeneric:Invisible-Pin|pin@8||-76|86|||||ART_message(D5G2;R)S1.8V native
+Ngeneric:Invisible-Pin|pin@9||-84.5|86|||||ART_message(D5G2;R)S2.5V native
+Ngeneric:Invisible-Pin|pin@10||-95|86|||||ART_message(D5G2;R)S3.3V native
+Ngeneric:Invisible-Pin|pin@11||1.5|86|||||ART_message(D5G2;R)Sweak high-threshold
+Ngeneric:Invisible-Pin|pin@12||10|86|||||ART_message(D5G2;R)Sweak standard
+Ngeneric:Invisible-Pin|pin@13||19.5|86|||||ART_message(D5G2;R)Sweak low-threshold
+Ngeneric:Invisible-Pin|pin@14||28.5|86|||||ART_message(D5G2;R)Sweak native
+Ipnp5;1{ic}|pnp2@0||-79.5|20|||D5G4;
+Ipnp10;1{ic}|pnp2@1||-79.5|13|||D5G4;
+Ipnp2;1{ic}|singlepn@2||-79.5|27|||D5G4;
+Iwire90;1{ic}|wire90@0||-110.5|37|||D5G4;|ATTR_L(D5G1;PUD)I100|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)S2|ATTR_width(D5G1;NPY-2;)S2.8
+Iwire90xcpl2;1{ic}|wire90xc@0||-110.5|30|||D5G4;|ATTR_L(D5G1;PUDY1;)I100|ATTR_layer(D5G1;NPY-0.5;)S2|ATTR_width(D5G1;NPY-1.5;)S2.8
+Iwire90xcpl3;1{ic}|wire90xc@1||-110.5|23|||D5G4;|ATTR_L(D5G1;PUDY1;)I100|ATTR_layer(D5G1;NPY-0.5;)S2|ATTR_width(D5G1;NPY-1.5;)S2.8
+IwireC;1{ic}|wireC@0||-95|26.5|||D0G4;|ATTR_L(D6G1.5;NOJPX1.5;Y0.5;)S100|ATTR_layer(D5G1;NPX3;Y-1.5;)I1|ATTR_width(D5G1;NPX3;Y-0.5;)I3
+IwireR;1{ic}|wireC@1||-95|34|||D0G4;|ATTR_L(D6G1.5;NOJPX1.5;Y0.5;)S100|ATTR_layer(D5G1;NPX3;Y-1.5;)I1|ATTR_width(D5G1;NPX3;Y-0.5;)I3
+Iwire_xcp_gnd;1{ic}|wire_xcp@0||-110.5|17|||D5G4;|ATTR_C(D5G1;NPURX2.5;Y-1;)S0.223f|ATTR_L(D5G1;PURY1;)I100|ATTR_LEWIRE(PUR)I1|ATTR_R(D5G1;NPURX-3;Y-1;)S24m|ATTR_layer(PUR)I2|ATTR_width(PUR)D2.8
+Iwire_xcpl_sides;1{ic}|wire_xcp@1||-110.5|12|||D5G4;|ATTR_C(D5G1;NPUCY-1;)S0.0000223p|ATTR_L(D5G1;PUDY1;)I100|ATTR_LEIGNORE(PUD)I1
+X
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