migrate jelib->delib

[fleet.git] / chips / marina / electric / purpleFive.delib / invCLK.sch

diff --git a/chips/marina/electric/purpleFive.delib/invCLK.sch b/chips/marina/electric/purpleFive.delib/invCLK.sch
new file mode 100644 (file)
index 0000000..dbf0730
--- /dev/null
+++ b/chips/marina/electric/purpleFive.delib/invCLK.sch
@@ -0,0 +1,23 @@
+HpurpleFive|8.10k
+
+# External Libraries:
+
+LredFive|redFive
+
+# Cell invCLK;1{sch}
+CinvCLK;1{sch}||schematic|1021415734000|1159375628155||ATTR_Delay(D5G1;HNPX-12;Y-5;)I100|ATTR_LEGATE(D5G1;HNPTX-12;Y-10;)I1|ATTR_LEPARALLGRP(D5G1;HNPTX-12;Y-6;)I-1|ATTR_X(D5G1;HNOJPX-12;Y-4;)SLE.getdrive()|ATTR_drive0(D5G1;HNPTX-12;Y-8;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-9;)Sstrong1|ATTR_su(D5G1;HNPTX-12;Y-7;)I-1|ATTR_verilog_template(D5G1;NTX6.5;Y-13;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||9.5|0||||
+NOff-Page|conn@1||-10|0||||
+IredFive:invCLK;1{ic}|invCLK@0||0|0|||D0G4;|ATTR_Delay(D5G1;NOJPX2;Y-2;)S@Delay|ATTR_X(D5G1.5;NOJPX1.5;Y2;)S@X|ATTR_drive0(OJP)S@drive0|ATTR_drive1(OJP)S@drive1
+IinvCLK;1{ic}|invCLK@1||24|19|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_LEGATE(P)I1|ATTR_LEPARALLGRP(P)I-1|ATTR_X(D5G1.5;NOJPX1.5;Y2;)SLE.getdrive()|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1|ATTR_su(P)I-1
+Ngeneric:Invisible-Pin|pin@0||-2|11.5|||||ART_message(D5G2;)S[should give equal R/F Delay]
+Ngeneric:Invisible-Pin|pin@1||-1|20.5|||||ART_message(D5G6;)S[inv3to1]
+Ngeneric:Invisible-Pin|pin@2||-2|15.5|||||ART_message(D5G2;)S[higher-threshold inverter]
+Ngeneric:Invisible-Pin|pin@3||13.5|-10|||||ART_message(D5G2;)S[X is drive strength,P drive strength is 1.5x N strength]
+Ngeneric:Invisible-Pin|pin@4||-2.5|13.5|||||ART_message(D5G2;)S[P to N width ratio is 3 to 1]
+Awire|net@0|||0|invCLK@0|in|-2.5|0|conn@1|y|-8|0
+Awire|net@1|||1800|invCLK@0|out|2.5|0|conn@0|a|7.5|0
+Ein||D5G2;|conn@1|a|I|ATTR_le(D5G1;NY-1.5;)F1.33
+Eout||D5G2;|conn@0|y|O|ATTR_le(D5G1;NY2;)F1.33
+X