migrate jelib->delib

[fleet.git] / chips / marina / electric / registersM.delib / addr2in60Cx15.sch

diff --git a/chips/marina/electric/registersM.delib/addr2in60Cx15.sch b/chips/marina/electric/registersM.delib/addr2in60Cx15.sch
new file mode 100644 (file)
index 0000000..26c54c4
--- /dev/null
+++ b/chips/marina/electric/registersM.delib/addr2in60Cx15.sch
@@ -0,0 +1,109 @@
+HregistersM|8.10k
+
+# External Libraries:
+
+LlatchesK|latchesK
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+# Cell addr2in60Cx15;1{sch}
+Caddr2in60Cx15;1{sch}||schematic|1189373179324|1238334870912|I
+Iaddr2in60Cx15;1{ic}|addr2in6@0||24|15|||D5G4;
+Iaddr2in60Cx7;1{ic}|addr2in6@1||24|0|||D5G4;
+Iaddr2in60Cx7;1{ic}|addr2in6@2||-24|0|||D5G4;
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||32|-6||||
+NOff-Page|conn@1||-32|-9||||
+NOff-Page|conn@2||-3|-15.5|||YRRR|
+NOff-Page|conn@3||-32|9|||XRR|
+IlatchesK:latch2in60C;1{ic}|latch2in@4||0|0|||D5G4;
+Ngeneric:Invisible-Pin|pin@0||1|38|||||ART_message(D5G6;)Saddr2in60Cx15
+Ngeneric:Invisible-Pin|pin@1||0|29|||||ART_message(D5G3;)Sies 29 December 2008
+Ngeneric:Invisible-Pin|pin@2||-1|33|||||ART_message(D5G4;)Sa complete address register
+NBus_Pin|pin@18||16|-1|-1|-1||
+NBus_Pin|pin@19||16|-5|-1|-1||
+NBus_Pin|pin@24||16|1|-1|-1||
+NBus_Pin|pin@25||16|5|-1|-1||
+NWire_Pin|pin@33||-7|1||||
+NWire_Pin|pin@34||-7|4||||
+NWire_Pin|pin@35||-7|-1||||
+NWire_Pin|pin@36||-7|-4||||
+NBus_Pin|pin@39||31|0|-1|-1||
+NBus_Pin|pin@40||31|-3|-1|-1||
+NWire_Pin|pin@41||7|0||||
+NWire_Pin|pin@42||7|-3||||
+NBus_Pin|pin@43||-26|-9|-1|-1||
+NBus_Pin|pin@44||-3|-9|-1|-1||
+NBus_Pin|pin@45||22|-9|-1|-1||
+NWire_Pin|pin@47||-2|6||||
+NWire_Pin|pin@48||-2|-6||||
+NBus_Pin|pin@49||-32|-1|-1|-1||
+NBus_Pin|pin@50||-32|-5|-1|-1||
+NBus_Pin|pin@51||-32|1|-1|-1||
+NBus_Pin|pin@52||-32|5|-1|-1||
+NBus_Pin|pin@53||-16|0|-1|-1||
+NBus_Pin|pin@54||-16|-3|-1|-1||
+NWire_Pin|pin@55||17.5|-12||||
+NWire_Pin|pin@56||17.5|-9||||
+NWire_Pin|pin@57||5.5|-12||||
+NWire_Pin|pin@58||5.5|-15.5||||
+NWire_Pin|pin@59||17.5|-18||||
+NWire_Pin|pin@60||17.5|-15||||
+NWire_Pin|pin@61||5.5|-18||||
+NWire_Pin|pin@62||5.5|-21.5||||
+NWire_Pin|pin@63||-24|-12|||X|
+NWire_Pin|pin@64||-24|-9|||X|
+NWire_Pin|pin@65||-12|-12|||X|
+NWire_Pin|pin@66||-12|-15.5|||X|
+NWire_Pin|pin@67||-24|-18|||X|
+NWire_Pin|pin@68||-24|-15|||X|
+NWire_Pin|pin@69||-12|-18|||X|
+NWire_Pin|pin@70||-12|-21.5|||X|
+IorangeTSMC090nm:wire90;1{ic}|wire90@3||-18.5|-12|X||D0G4;|ATTR_L(D5G1;PUD)S2330|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@4||-18.5|-18|X||D0G4;|ATTR_L(D5G1;PUD)S2330|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@5||12|-18|||D0G4;|ATTR_L(D5G1;PUD)S2330|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@6||12|-12|||D0G4;|ATTR_L(D5G1;PUD)S2330|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+Abus|ainA[1:7]|D5G2;|-0.5|IJ900|pin@18||16|-1|pin@19||16|-5
+Abus|ainA[8:14]|D5G2;|-0.5|IJ900|pin@49||-32|-1|pin@50||-32|-5
+Awire|ainA[TT]|D5G2;||900|pin@35||-7|-1|pin@36||-7|-4
+Abus|ainB[1:7]|D5G2;|-0.5|IJ2700|pin@24||16|1|pin@25||16|5
+Abus|ainB[8:14]|D5G2;|-0.5|IJ2700|pin@51||-32|1|pin@52||-32|5
+Awire|ainB[TT]|D5G2;||2700|pin@33||-7|1|pin@34||-7|4
+Abus|aout[1:7]|D5G2;|-0.5|IJ900|pin@39||31|0|pin@40||31|-3
+Abus|aout[8:14]|D5G2;|-0.5|IJ900|pin@53||-16|0|pin@54||-16|-3
+Awire|aout[TT]|D5G2;||900|pin@41||7|0|pin@42||7|-3
+Abus|fire[A1,B1]|D5G2;|-0.5|IJ900|addr2in6@2|fire[A,B]|-26|-3|pin@43||-26|-9
+Awire|fire[A1]|D5G2;||2700|pin@63||-24|-12|pin@64||-24|-9
+Abus|fire[A2,B2]|D5G2;|-0.5|IJ2700|pin@45||22|-9|addr2in6@1|fire[A,B]|22|-3
+Awire|fire[A2]|D5G2;||2700|pin@55||17.5|-12|pin@56||17.5|-9
+Awire|fire[A2]|D5G2;||900|latch2in@4|hcl[A]|-2|-3|pin@48||-2|-6
+Awire|fire[A]|D5G2;||900|pin@57||5.5|-12|pin@58||5.5|-15.5
+Awire|fire[A]|D5G2;||900|pin@65||-12|-12|pin@66||-12|-15.5
+Awire|fire[B1]|D5G2;||2700|pin@67||-24|-18|pin@68||-24|-15
+Awire|fire[B2]|D5G2;||2700|pin@59||17.5|-18|pin@60||17.5|-15
+Awire|fire[B2]|D5G2;||2700|latch2in@4|hcl[B]|-2|3|pin@47||-2|6
+Awire|fire[B]|D5G2;||900|pin@61||5.5|-18|pin@62||5.5|-21.5
+Awire|fire[B]|D5G2;||900|pin@69||-12|-18|pin@70||-12|-21.5
+Abus|net@20||-0.5|IJ0|addr2in6@1|ainA[1:14]|21|-1|pin@18||16|-1
+Abus|net@30||-0.5|IJ0|addr2in6@1|ainB[1:14]|21|1|pin@24||16|1
+Awire|net@39|||0|latch2in@4|inB[1]|-3|1|pin@33||-7|1
+Awire|net@41|||0|latch2in@4|inA[1]|-3|-1|pin@35||-7|-1
+Abus|net@45||-0.5|IJ1800|addr2in6@1|aout[1:14]|27|0|pin@39||31|0
+Awire|net@47|||1800|latch2in@4|out[1]|3|0|pin@41||7|0
+Abus|net@48||-0.5|IJ900|pin@44||-3|-9|conn@2|y|-3|-13.5
+Abus|net@70||-0.5|IJ1800|addr2in6@2|aout[1:14]|-21|0|pin@53||-16|0
+Abus|net@81||-0.5|IJ0|addr2in6@2|ainA[1:14]|-27|-1|pin@49||-32|-1
+Abus|net@82||-0.5|IJ0|addr2in6@2|ainB[1:14]|-27|1|pin@51||-32|1
+Awire|net@83|||1800|wire90@6|b|14.5|-12|pin@55||17.5|-12
+Awire|net@84|||0|wire90@6|a|9.5|-12|pin@57||5.5|-12
+Awire|net@85|||1800|wire90@5|b|14.5|-18|pin@59||17.5|-18
+Awire|net@86|||0|wire90@5|a|9.5|-18|pin@61||5.5|-18
+Awire|net@87|||0|wire90@3|b|-21|-12|pin@63||-24|-12
+Awire|net@88|||1800|wire90@3|a|-16|-12|pin@65||-12|-12
+Awire|net@89|||0|wire90@4|b|-21|-18|pin@67||-24|-18
+Awire|net@90|||1800|wire90@4|a|-16|-18|pin@69||-12|-18
+EinA[1:37]|ainA[TT,1:14]|D4G2;|conn@1|a|I
+EinB[1:37]|ainB[TT,1:14]|D4G2;|conn@3|a|I
+Eout[1:37]|aout[TT,1:14]|D6G2;|conn@0|y|O
+Etake[A,B]|fire[A,B]|D4G2;|conn@2|a|I
+X