migrate jelib->delib

[fleet.git] / chips / marina / electric / stagesM.delib / rqDockStage.sch

diff --git a/chips/marina/electric/stagesM.delib/rqDockStage.sch b/chips/marina/electric/stagesM.delib/rqDockStage.sch
new file mode 100644 (file)
index 0000000..3b3b93a
--- /dev/null
+++ b/chips/marina/electric/stagesM.delib/rqDockStage.sch
@@ -0,0 +1,118 @@
+HstagesM|8.10k
+
+# External Libraries:
+
+LdriversM|driversM
+
+LoneHotM|oneHotM
+
+LorangeTSMC090nm|orangeTSMC090nm
+
+LregistersM|registersM
+
+LscanM|scanM
+
+LwiresL|wiresL
+
+# Cell rqDockStage;1{sch}
+CrqDockStage;1{sch}||schematic|1227457806942|1243246708862|I
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-9.5|3|||Y|
+NOff-Page|conn@1||11|0|||Y|
+NOff-Page|conn@2||-9.5|0|||Y|
+NOff-Page|conn@6||12.5|-36||||
+NOff-Page|conn@7||-11|-33.5||||
+NOff-Page|conn@8||-11.5|-39||||
+NOff-Page|conn@11||-10|-3|||Y|
+NOff-Page|conn@12||0|-17|||YR|
+NOff-Page|conn@14||15|12|||Y|
+NOff-Page|conn@15||60|12||||
+IregistersM:ins2in20Ax36;1{ic}|ins2in20@0||0.5|-36|Y||D5G4;
+IdriversM:latchDriver60;1{ic}|latchDri@2||-15|-18|RRR||D5G4;
+IdriversM:latchDriver60;1{ic}|latchDri@3||15|-18|YR||D5G4;
+NWire_Pin|pin@2||6|-6|||X|
+NWire_Pin|pin@3||-6|-6|||XRR|
+NWire_Pin|pin@5||-6|-12|||X|
+NWire_Pin|pin@6||6|-12|||X|
+NWire_Pin|pin@7||-15|-12||||
+NWire_Pin|pin@8||15|-12||||
+Ngeneric:Invisible-Pin|pin@9||0|34|||||ART_message(D5G4;)S[the requeue stage,with scan chain]
+Ngeneric:Invisible-Pin|pin@10||-1.5|42.5|||||ART_message(D5G6;)SrqDockStage
+NWire_Pin|pin@26||15|-27||||
+NWire_Pin|pin@30||-15|-27||||
+NBus_Pin|pin@51||-6|-39|-1|-1||
+NBus_Pin|pin@52||-6|-37|-1|-1||
+NBus_Pin|pin@53||-6|-33.5|-1|-1||
+NBus_Pin|pin@54||-6|-35|-1|-1||
+NBus_Pin|pin@67||0|-8|-1|-1||
+NBus_Pin|pin@68||-1.5|-25.5|-1|-1|Y|
+NWire_Pin|pin@79||-2|17||||
+NWire_Pin|pin@80||25|1||||
+NBus_Pin|pin@81||2|13|-1|-1||
+NWire_Pin|pin@83||35.5|-12||||
+NWire_Pin|pin@84||41.5|-12||||
+NWire_Pin|pin@85||47|-11||||
+NBus_Pin|pin@86||41.5|8|-1|-1||
+NBus_Pin|pin@87||34|12|-1|-1||
+NBus_Pin|pin@88||34|18|-1|-1||
+NWire_Pin|pin@89||57|-1.5||||
+NWire_Pin|pin@90||57|5||||
+NWire_Pin|pin@91||29|-1.5||||
+NWire_Pin|pin@92||29|2||||
+Ngeneric:Invisible-Pin|pin@93||-3|25.5|||||ART_message(D5FLeave alone;G3;)Sies 3 April 2009
+IoneHotM:reQueue;1{ic}|reQueue@0||0|0|||D5G4;
+IrqDockStage;1{ic}|rqDockSt@0||-39|15|||D5G4;
+IscanM:scanEx1;1{ic}|scanEx1@0||27|12|YRRR||D5G4;
+IscanM:scanEx3plain;1{ic}|scanEx3p@1||43.5|-1.5|XR||D5G4;
+IwiresL:tranCap;1{ic}|tranCap@0||-13|14|||D5G4;
+IorangeTSMC090nm:wire90;1{ic}|wire90@0||10.5|-12|RR||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1336.1999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@1||-10.5|-12|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D1307.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
+Abus|fire[E,R]|D5G2;|-0.5|IJ900|reQueue@0|fire[E,P]|0|-5|pin@67||0|-8
+Awire|fire[E]|D5G2;||2700|pin@5||-6|-12|pin@3||-6|-6
+Awire|fire[R]|D5G2;||2700|pin@6||6|-12|pin@2||6|-6
+Awire|mc|D5G2;||2700|reQueue@0|mc|-2|5|pin@79||-2|17
+Awire|net@3|||0|wire90@1|a|-13|-12|pin@7||-15|-12
+Awire|net@4|||900|pin@7||-15|-12|latchDri@2|in|-15|-14
+Awire|net@5|||1800|wire90@1|b|-8|-12|pin@5||-6|-12
+Awire|net@6|||1800|pin@6||6|-12|wire90@0|b|8|-12
+Awire|net@7|||1800|wire90@0|a|13|-12|pin@8||15|-12
+Awire|net@8|||900|pin@8||15|-12|latchDri@3|in|15|-14
+Abus|net@59||-0.5|IJ1800|conn@8|y|-9.5|-39|pin@51||-6|-39
+Abus|net@60||-0.5|IJ2700|pin@51||-6|-39|pin@52||-6|-37
+Abus|net@62||-0.5|IJ1800|conn@7|y|-9|-33.5|pin@53||-6|-33.5
+Abus|net@63||-0.5|IJ900|pin@53||-6|-33.5|pin@54||-6|-35
+Abus|net@80||-0.5|IJ0|reQueue@0|pred[EPI,TAIL]|-4|3|conn@0|y|-7.5|3
+Awire|net@81|||1800|reQueue@0|succ|4|0|conn@1|a|9|0
+Abus|net@90||-0.5|IJ1800|conn@11|y|-8|-3|reQueue@0|pred_1[HEAD,RQA]|-4|-3
+Abus|net@91||-0.5|IJ1800|ins2in20@0|out[1:36]|3.5|-36|conn@6|a|10.5|-36
+Abus|net@92||-0.5|IJ0|ins2in20@0|inB[1:36]|-2.5|-37|pin@52||-6|-37
+Abus|net@93||-0.5|IJ1800|pin@54||-6|-35|ins2in20@0|inA[1:36]|-2.5|-35
+Abus|net@94||-0.5|IJ1800|conn@2|y|-7.5|0|reQueue@0|od[HEAD,BODY]|-4|0
+Abus|net@111||-0.5|IJ1800|conn@14|y|17|12|scanEx1@0|sir[1:9]|25|12
+Awire|net@118|||0|scanEx1@0|mc|26|17|pin@79||-2|17
+Abus|net@123||-0.5|IJ1800|scanEx1@0|sor[1:9]|29|12|pin@87||34|12
+Awire|net@125|||1800|scanEx3p@1|sout|51|-1.5|pin@89||57|-1.5
+Awire|net@127|||0|scanEx3p@1|sin|35.5|-1.5|pin@91||29|-1.5
+Abus|s[1:4]|D5G2;|-0.5|IJ2700|reQueue@0|s[1:6]|2|6|pin@81||2|13
+Awire|s[1]|D5G2;||900|scanEx1@0|dIn[1]|25|7|pin@80||25|1
+Awire|s[2]|D5G2;||900|scanEx3p@1|dIn[1]|35.5|-6.5|pin@83||35.5|-12
+Awire|s[3]|D5G2;||900|scanEx3p@1|dIn[2]|41.5|-6.5|pin@84||41.5|-12
+Awire|s[4]|D5G2;||900|scanEx3p@1|dIn[3]|47|-6.5|pin@85||47|-11
+Awire|sin|D5G2;||2700|pin@91||29|-1.5|pin@92||29|2
+Abus|sin,sor[2:9]|D5G2;|-0.5|IJ2700|pin@87||34|12|pin@88||34|18
+Abus|sir[2,3,5]|D5G2;|-0.5|IJ2700|scanEx3p@1|sir[2,3,5]|41.5|2.5|pin@86||41.5|8
+Awire|sor[1]|D5G2;||2700|pin@89||57|-1.5|pin@90||57|5
+Abus|take[E,P]|D5G2;|-0.5|IJ2700|ins2in20@0|hcl[B][1]|-1.5|-33|pin@68||-1.5|-25.5
+Awire|take[E]|D5G2;||900|latchDri@2|out|-15|-22|pin@30||-15|-27
+Awire|take[P]|D5G2;||900|latchDri@3|out|15|-22|pin@26||15|-27
+EpredA|epi[TAIL,OTHER]|D4G2;|conn@0|a|I
+EinA[1:36]|inE[1:36]|D4G2;|conn@7|a|I
+EinB[1:36]|inP[1:36]|D4G2;|conn@8|a|I
+EpredB|od[HEAD,ABORT,OTHER]|D4G2;|conn@2|a|I
+Epred[RQM,DRAIN]|ps[skip,do]|D4G2;|conn@11|a|I
+Eout[1:36]|rq[1:36]|D6G2;|conn@6|y|O
+Esucc|rq[succ]|D6G2;|conn@1|y|O
+Esir[1:9]||D4G2;|conn@14|a|I
+Esor[1:9]||D6G2;|conn@15|y|O
+Esucc_1|take[E,P]|D6G2;|conn@12|y|O
+X