migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / orange40nm.delib / NMOSf_io18.sch

diff --git a/chips/omegaCounter/40nm/electric/orange40nm.delib/NMOSf_io18.sch b/chips/omegaCounter/40nm/electric/orange40nm.delib/NMOSf_io18.sch
new file mode 100644 (file)
index 0000000..a3278fd
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/orange40nm.delib/NMOSf_io18.sch
@@ -0,0 +1,27 @@
+Horange40nm|8.10k
+
+# Cell NMOSf_io18;1{sch}
+CNMOSf_io18;1{sch}||schematic|1021415734000|1245272160722||ATTR_Delay(D5G1;HNPTX-9;Y-15.75;)I15|ATTR_L(D5FLeave alone;G1;HNOLPX-9;Y-11.5;)S15|ATTR_M1(D5G1;HNOLPX-9.25;Y-15;)S1|ATTR_NF(D5G1;HNOLPX-9;Y-13;)S1|ATTR_W(D5FLeave alone;G1;HNOLPX-9;Y-10.5;)S32|ATTR_CDL_template(D5G1;NTX0.5;Y-29;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template(D5G1;NTX4;Y-24.5;)SXM$(node_name) $(d) $(g) $(s) gnd nch_18_mac w='$(W)*10n' l='$(L)*10n' nf='$(NF)' m='$(M1)'|ATTR_SPICE_template_calibre(D5G1;NTX1;Y-31;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*0.01u' L='$(L)*0.01u' M='$(M1)'|ATTR_SPICE_template_smartspice(D5G1;NTX0.5;Y-22.5;)SM$(node_name) $(d) $(g) $(s) gnd nch_18 W='$(W)*10n' L='$(L)*10n' NF='$(NF)' M='$(M1)'|ATTR_verilog_template(D5G1;NTX-1;Y-26.5;)Stranif1 #($(Delay)) $(node_name) ($(d), $(s), $(g));|prototype_center()I[0,0]
+INMOSf_io18;1{ic}|NMOSf_io@0||28|0.5|||D0G4;|ATTR_Delay(P)I100|ATTR_L(D5FLeave alone;G1;NOLPX4;Y0.5;)S15|ATTR_M1(D5G1;NOLPX4;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX4;Y-0.5;)S1|ATTR_W(D5FLeave alone;G1;NOLPX4;Y1.5;)S32
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||6|-16.5||||
+NOff-Page|conn@1||6.5|0||||
+NOff-Page|conn@2||-16.5|-8||||
+NGround|gnd@0||5|-11||||
+N4-Port-Transistor|nmos4p@0||-2|-8|||R||ATTR_M(D5G1;NOLX0.5;Y-4;)S@M1|ATTR_length(D5FLeave alone;G1;OLX-1;Y1;)S"P(\"L\")"|ATTR_width(D5FLeave alone;G1.5;OLX0.5;Y-1;)S"P(\"W\")"|SIM_spice_model(D5G1;X1.5;Y-3;)Snch_18
+NWire_Pin|pin@0||0|-16.5||||
+NWire_Pin|pin@1||0|0||||
+Ngeneric:Invisible-Pin|pin@2||1.5|18|||||ART_message(D5G6;)SNMOSf_io18
+Ngeneric:Invisible-Pin|pin@3||1.5|11.5|||||ART_message(D5G2;)S3-terminal NMOS device for 1.8V I/O pads
+Ngeneric:Invisible-Pin|pin@4||3|8|||||ART_message(D5G2;)Sminimum length for 1.8V thick-oxide devices is 15 (0.15um)
+Ngeneric:Invisible-Pin|pin@5||3|6|||||ART_message(D5G2;)Sminimum width is 32 (0.32um)
+Awire|net@0|||0|conn@1|a|4.5|0|pin@1||0|0
+Awire|net@1|||0|nmos4p@0|g|-3|-8|conn@2|y|-14.5|-8
+Awire|net@2|||900|nmos4p@0|s|0|-10|pin@0||0|-16.5
+Awire|net@3|||1800|pin@0||0|-16.5|conn@0|a|4|-16.5
+Awire|net@4|||900|pin@1||0|0|nmos4p@0|d|0|-6
+Awire|net@5|||1800|nmos4p@0|b|0|-9|gnd@0||5|-9
+Ed||D5G2;|conn@1|y|B
+Eg||D5G2;|conn@2|a|I
+Es||D5G2;|conn@0|y|B
+X