migrate jelib->delib

[fleet.git] / chips / omegaCounter / 40nm / electric / redFive.delib / nand2LT.sch

diff --git a/chips/omegaCounter/40nm/electric/redFive.delib/nand2LT.sch b/chips/omegaCounter/40nm/electric/redFive.delib/nand2LT.sch
new file mode 100644 (file)
index 0000000..598303f
--- /dev/null
+++ b/chips/omegaCounter/40nm/electric/redFive.delib/nand2LT.sch
@@ -0,0 +1,49 @@
+HredFive|8.10k
+
+# Cell nand2LT;1{sch}
+Cnand2LT;1{sch}||schematic|1021415734000|1248729055117||ATTR_Delay(D5G1;HNPX-13.5;Y-16;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-13.5;Y-15;)S1|ATTR_drive0(D5G1;HNPTX-13.5;Y-17;)Sstrong0|ATTR_drive1(D5G1;HNPTX-13.5;Y-18;)Sstrong1|ATTR_verilog_template(D5G1;NTX26.5;Y-17;)Snand ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(ina), $(inb));|prototype_center()I[0,0]
+IPMOS;1{ic}|PMOS@2||6|4|YRR||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)S@X/2.
+IPMOS;1{ic}|PMOS@3||-5|4|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5G1.5;NOLPX3.5;Y0.5;)S@X/2.
+Ngeneric:Facet-Center|art@0||0|0||||AV
+NOff-Page|conn@0||-14.5|-9||||
+NOff-Page|conn@1||17|-5|||RR|
+NOff-Page|conn@2||17|0||||
+Inand2LT;1{ic}|nand2LT@0||29|14.5|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.5;Y2.5;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+Inms2b;1{ic}|nms2@0||0|-9|||D0G4;|ATTR_Delay(D5G1;NOJPX5.5;Y-0.5;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX-3.75;Y2.5;)S@X
+Ngeneric:Invisible-Pin|pin@0||36.5|-10|||||ART_message(D5G2;)S[X is drive strength,The pull-down is twice as strong as,one pull-up; or both pull-ups together,are as strong as the pull-down]
+NWire_Pin|pin@1||-9.5|4||||
+NWire_Pin|pin@2||-5|0||||
+NWire_Pin|pin@3||-9.5|-9||||
+NWire_Pin|pin@4||6|0||||
+NWire_Pin|pin@5||11|4||||
+NWire_Pin|pin@6||11|-5||||
+Ngeneric:Invisible-Pin|pin@7||3.5|25|||||ART_message(D5G6;)S[nand2LT]
+NWire_Pin|pin@8||-5|7.5||||
+NWire_Pin|pin@9||6|7.5||||
+Ngeneric:Invisible-Pin|pin@10||2|20|||||ART_message(D5G2;)S[LO-threshold NAND]
+Ngeneric:Invisible-Pin|pin@11||2.5|18|||||ART_message(D5G2;)S[P to N width ratio is 1 to 2]
+Ngeneric:Invisible-Pin|pin@12||3|16|||||ART_message(D5G2;)S[Sized assuming both inputs go low together]
+NWire_Pin|pin@13||0|0||||
+NPower|pwr@0||-5|10.5||||
+Awire|net@0|||0|pin@6||11|-5|nms2@0|g2|3|-5
+Awire|net@1|||900|pin@13||0|0|nms2@0|d|0|-3
+Awire|net@2|||0|nms2@0|g|-3|-9|pin@3||-9.5|-9
+Awire|net@3|||2700|pin@3||-9.5|-9|pin@1||-9.5|4
+Awire|net@4|||0|pin@3||-9.5|-9|conn@0|y|-12.5|-9
+Awire|net@5|||2700|pin@6||11|-5|pin@5||11|4
+Awire|net@6|||1800|pin@6||11|-5|conn@1|y|15|-5
+Awire|net@7|||0|pin@9||6|7.5|pin@8||-5|7.5
+Awire|net@8|||2700|pin@8||-5|7.5|pwr@0||-5|10.5
+Awire|net@9|||1800|pin@4||6|0|conn@2|a|15|0
+Awire|net@10|||2700|pin@4||6|0|PMOS@2|d|6|2
+Awire|net@11|||1800|PMOS@2|g|9|4|pin@5||11|4
+Awire|net@12|||2700|PMOS@2|s|6|6|pin@9||6|7.5
+Awire|net@13|||2700|pin@2||-5|0|PMOS@3|d|-5|2
+Awire|net@14|||1800|pin@1||-9.5|4|PMOS@3|g|-8|4
+Awire|net@15|||900|pin@8||-5|7.5|PMOS@3|s|-5|6
+Awire|net@16|||0|pin@13||0|0|pin@2||-5|0
+Awire|net@17|||0|pin@4||6|0|pin@13||0|0
+Eina||D5G2;|conn@0|a|I
+Einb||D5G2;|conn@1|a|I
+Eout||D5G2;|conn@2|y|O
+X