# header information:
-HredFive|8.10c|USER_electrical_units()I70464
+HredFive|8.10h|USER_electrical_units()I70464
# Views:
Vicon|ic
# Tools:
Ouser|DefaultTechnology()Scmos90|SchematicTechnology()Scmos90
Oio|GDSOutputConvertsBracketsInExports()BF|GDSWritesExportPins()BT
+OSTA|GlobalSDCCommands()S"\n### 4 GHz clock setup\ncreate_clock -period 0.250 -name clk -waveform \"0 0.125\" clk\nset_clock_uncertainty -setup 0.010 clk\nset_clock_uncertainty -hold 0.010 clk\nset_propagated_clock clk\nset_clock_transition -rise 0.030 clk\nset_clock_transition -fall 0.030 clk\n#set_driving_cell -lib_cell inv_X008_0 clk\n\n### remove scan path from timing\nset_false_path -through */so\nset_false_path -from {sin}\nset_false_path -from {scanEn}\nset_false_path -to {sout}\n"
# Technologies:
Tcmos90|"GDS(ST)LayerForPad-FrameINcmos90"()S43|"GDS(TSMC)LayerForPad-FrameINcmos90"()S43
X
# Cell PMOS;2{sch}
-CPMOS;2{sch}||schematic|1021415734000|1249583164934||ATTR_Delay(D5G1;HNPX-8.5;Y1.25;)I100|ATTR_X(D5G1;HNPX-8.5;Y2.75;)I1|prototype_center()I[0,0]
+CPMOS;2{sch}||schematic|1021415734000|1253517339112||ATTR_Delay(D5G1;HNPX-8.5;Y1.25;)I100|ATTR_X(D5G1;HNPX-8.5;Y2.75;)I1|prototype_center()I[0,0]
IPMOS;1{ic}|PMOS@0||15.25|12.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-1;)S10|ATTR_X(D5G1.5;NPX3.5;Y1;)I1
Iorange40nm:PMOSf;1{ic}|PMOSf@1||0|7|||D0G4;|ATTR_Delay(OJP)S@Delay|ATTR_L(D5G1;NOJPX3.5;Y0.5;)S4|ATTR_M1(D5G1;NOLPX3.5;Y-1.5;)S1|ATTR_NF(D5G1;NOLPX3.5;Y-0.5;)S@X <= 6 ? 1 : @X <= 12 ? 2 : @X <= 18 ? 3 : @X <= 24 ? 4 : @X <= 30 ? 5 : @X <= 36 ? 6 : @X <= 42 ? 7 : @X/6|ATTR_W(D6G1;NOJPX2;Y1.5;)S24*@X
Ngeneric:Facet-Center|art@0||0|0||||AV