cleanup, add Generator for verilog netlists

[fleet.git] / ships / Alu1.ship

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index 6818560..c80bafe 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -38,9 +38,9 @@ ABS:
 
 == FleetSim ==============================================================
 == FPGA ==============================================================
-  reg                    have_a;
+  reg                       have_a;
   reg [(`PACKET_WIDTH-1):0] reg_a;
-  reg                    have_op;
+  reg                       have_op;
   reg [(`PACKET_WIDTH-1):0] reg_op;
   reg [(`PACKET_WIDTH-1):0] extrabits;