data_to_host_write_enable <= 0;
if (force_reset == 1) begin
force_reset <= 0;
- data_to_host_write_enable <= 1;
+ //data_to_host_write_enable <= 1;
credits = 0;
count_in <= 0;
count_out <= 0;
.SEL(sel),
.DRCK(drck));
- wire [9:0] din;
wire [9:0] dout;
reg [9:0] dout_r;
+ reg [9:0] din;
+ wire write_o;
+ wire read_o;
wire strobe_o;
- assign din = 10'h71;
wire ack_i;
assign ack_i = 1;
.res_i (rst),
.strobe_o (strobe_o),
- .read_o (),
+ .read_o (read_o),
.write_o (write_o),
.ack_i (ack_i),
.cs_o (),
.addr_o (),
- .din_i (dout_r),
+ .din_i (din),
.dout_o (dout)
);
- always @(posedge clk) begin
- if (strobe_o)
- dout_r <= dout;
- end
+ wire strobe_write;
+ assign strobe_write = strobe_o & write_o;
+ wire strobe_read;
+ assign strobe_read = strobe_o & read_o;
+
+ reg strobe_write_was_high;
+ initial strobe_write_was_high = 0;
wire break_i;
reg send_k;
reg data_to_fleet_read_enable;
reg [7:0] force_reset;
+ reg data_to_host_full_bit;
+
assign clk_out = clk_pin;
wire sio_ce;
count_out <= 0;
force_reset <= 0;
credits = 0;
+ data_to_host_full_bit <= 0;
`reset
end else begin
`cleanup
+ if (strobe_read) begin
+ din <= { 1'b0, data_to_host_full_bit, data_to_host };
+ data_to_host_full_bit <= 0;
+ end
+
// fpga -> host
data_to_host_write_enable <= 0;
if (force_reset == 1) begin
`reset
end else if (force_reset != 0) begin
force_reset <= force_reset-1;
- end else if (count_out==0 && `in_full) begin
+ end else if (count_out==0 && `in_full && data_to_host_full_bit==0) begin
`drain_in
data_to_host_full_word <= in_d;
count_out <= 8;
- end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
+ end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0 && data_to_host_full_bit==0) begin
data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
data_to_host_full_word <= (data_to_host_full_word >> 6);
- data_to_host_write_enable <= 1;
+ data_to_host_full_bit <= 1;
count_out <= count_out-1;
credits = credits - 1;
end
// host -> fpga
data_to_fleet_read_enable <= 0;
+
+ if (!strobe_write && strobe_write_was_high) begin
+ strobe_write_was_high <= 0;
+
+ end else if (strobe_write && !strobe_write_was_high && (force_reset == 0)) begin
+ strobe_write_was_high <= 1;
+ // command 0: data
+ if (dout[7:6] == 2'b00 && `out_empty) begin
+ out_d <= { out_d[43:0], dout[5:0] };
+ if (count_in==9) begin
+ count_in <= 0;
+ `fill_out
+ end else begin
+ count_in <= count_in+1;
+ end
+
+ // command 1: flow control credit
+ end else if (dout[7:6] == 2'b01) begin
+ credits = credits + dout[5:0];
+
+ // command 3: reset (and echo back reset code)
+ end else if (dout[7:6] == 2'b11) begin
+ data_to_host <= dout[7:0];
+ data_to_host_full_bit <= 1;
+ force_reset <= 255;
+
+ end
+
+ end else
if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
// Note: if the switch fabric refuses to accept a new item,