re-enable bitgen DRC, disable unused ddr2 signals

[fleet.git] / src / edu / berkeley / fleet / fpga / main.v

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index 921a40e..069e898 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -19,7 +19,7 @@ module main
   ddr1_DM_pin,
   ddr1_DQS,
   ddr1_DQ,
-
+/*
   ddr2_ODT_pin,
   ddr2_Clk_pin,
   ddr2_Clk_n_pin,
@@ -34,7 +34,7 @@ module main
   ddr2_DQS,
   ddr2_DQS_n,
   ddr2_DQ,
-
+*/
   vga_psave,
   vga_hsync,
   vga_vsync,
@@ -67,7 +67,7 @@ module main
   output [3:0]  ddr1_DM_pin;
   inout  [3:0]  ddr1_DQS;
   inout  [31:0] ddr1_DQ;
-
+/*
   output        ddr2_ODT_pin;
   output        ddr2_Clk_pin;
   output        ddr2_Clk_n_pin;
@@ -82,7 +82,7 @@ module main
   inout  [7:0]  ddr2_DQS;
   inout  [7:0]  ddr2_DQS_n;
   inout  [63:0] ddr2_DQ;
-
+*/
   wire  [31:0]  dram_addr;
   wire          dram_addr_r;
   wire          dram_addr_a;
@@ -95,6 +95,7 @@ module main
   wire          dram_read_data_empty;
   wire   [1:0]  dram_read_data_latency;
 
+/*
   wire  [31:0]  ddr2_addr;
   wire          ddr2_addr_r;
   wire          ddr2_addr_a;
@@ -106,6 +107,7 @@ module main
   wire          ddr2_read_data_pop;
   wire          ddr2_read_data_empty;
   wire   [1:0]  ddr2_read_data_latency;
+*/
 
   output vga_psave;
   output vga_hsync;