major overhaul of FPGA code to support both ML509 and Bee2 at the same time
[fleet.git] / src / edu / berkeley / fleet / fpga / verilog / Verilog.java
index 31d96ab..44d02e5 100644 (file)
@@ -654,7 +654,7 @@ public class Verilog {
                 if (!fix) throw new RuntimeException();
             boolean isRoot = name.equals("main");
             pw.print("module "+name);
-            pw.println(isRoot ? "(clk_pin, rst_pin " : "(clk, rst ");
+            pw.println(isRoot ? "(rst_pin " : "(clk, rst ");
             for(String name : portorder) pw.println("    , " + ports.get(name).getInterface());
             for (InstantiatedModule im : this.instantiatedModules.values())
                 for(PercolatedPort pp : im.module.percolatedPorts)
@@ -664,15 +664,11 @@ public class Verilog {
             pw.println();
 
             if (isRoot) {
-                pw.println("  input clk_pin;");
                 pw.println("  input rst_pin;");
                 pw.println("  wire clk;");
                 pw.println("  wire clk_fb;");
                 pw.println("  wire clk_unbuffered;");
-                pw.println("  assign clk_unbuffered = clk_pin;");
-                //pw.println("  assign clk = clk_pin;");
 
-                pw.println("  BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));");
                 /*
                 pw.println("  DCM");
                 pw.println("   #(");
@@ -712,6 +708,8 @@ public class Verilog {
             if (isRoot) {
                 pw.println("  assign rst    = rst_out;");
                 pw.println("  assign rst_in = !rst_pin;");
+                pw.println("  BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));");
+                pw.println("  assign clk_unbuffered = clk_out;");
             }
 
             for(String name : ports.keySet()) pw.println("    " + ports.get(name).getDeclaration());