cleanup, add Generator for verilog netlists

[fleet.git] / src / edu / berkeley / fleet / slipway / funnel.v

diff --git a/src/edu/berkeley/fleet/slipway/funnel.v b/src/edu/berkeley/fleet/slipway/funnel.v
index d82b9ae..e2f5f62 100644 (file)
--- a/src/edu/berkeley/fleet/slipway/funnel.v
+++ b/src/edu/berkeley/fleet/slipway/funnel.v
@@ -1,41 +1,51 @@
-`include "macros.v"
+module funnel(clk
+    , out_r_, out_a, out_
+    , in1_r, in1_a_, in1
+    , in2_r, in2_a_, in2
+   );
 
-module funnel(clk,
-              out_r_, out_a,  out_d_,
-              in1_r,  in1_a_, in1_d,
-              in2_r,  in2_a_, in2_d
-              );
+    input clk;
+    output out_r_;
+input out_a;
+output [47:0]out_;
+reg out_r;
+initial out_r = 0;
+reg    [47:0]out;
+initial out = 0;
 
-  input                  clk;
-  reg                    last;
-  initial                last=0;
-  reg                    full;
-  initial                full=0;
+    input in2_r;
+output in2_a_;
+input [47:0]in2;
+reg in2_a;
+initial in2_a = 0;
 
-  `input(in1_r,   in1_a, in1_a_, [(`PACKET_WIDTH-1):0], in1_d)
-  `input(in2_r,   in2_a, in2_a_, [(`PACKET_WIDTH-1):0], in2_d)
-  `output(out_r, out_r_, out_a,  [(`PACKET_WIDTH-1):0], out_d_)
-  `defreg(out_d_, [(`PACKET_WIDTH-1):0], out_d)
+    input in1_r;
+output in1_a_;
+input [47:0]in1;
+reg in1_a;
+initial in1_a = 0;
 
-  always @(posedge clk) begin
-    if (full) begin
-      `onwrite(out_r, out_a)
-        full = 0;
-      end
-    end else begin
-      last = ~last;
-      if (last) begin
-        `onread(in1_r, in1_a)
-          full  = 1;
-          out_d = in1_d;
-        end
-      end else begin
-        `onread(in2_r, in2_a)
-          full  = 1;
-          out_d = in2_d;
-        end
-      end
-    end
-  end
-   
+    assign out_r_ = out_r;
+assign out_ = out;
+
+    assign in2_a_ = in2_a;
+
+    assign in1_a_ = in1_a;
+
+always @(posedge clk) begin
+if (out_r && out_a) begin out_r<=0;  end
+if (!in1_r && in1_a) in1_a<=0;
+if (!in2_r && in2_a) in2_a<=0;
+if (1 && in2_r && !in2_a && !out_r && !out_a) begin 
+in2_a <= 1;
+out_r <= 1;
+out  = in2;
+end else 
+if (1 && in1_r && !in1_a && !out_r && !out_a) begin 
+in1_a <= 1;
+out_r <= 1;
+out  = in1;
+end else 
+ begin end
+end
 endmodule