remove Memory.{outIhorn,inStride,inCount} ports

diff --git a/ships/Memory.ship b/ships/Memory.ship
index 4718196..c86e9ae 100644 (file)
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -5,11 +5,8 @@ data  in:    inCBD
 data  in:    inAddrRead
 data  in:    inAddrWrite
 data  in:    inDataWrite
-data  in:    inStride
-data  in:    inCount
 
 data  out:   out
-data  out:   outIhorn
 
 == TeX ==============================================================
 
@@ -144,16 +141,24 @@ sequence guarantee problem mentioned in the previous paragraph.
 
 == FPGA ==============================================================
 
-  reg [(`CODEBAG_SIZE_BITS-1):0]  cursor;
-  reg                             write_flag;
+  wire [(`DATAWIDTH-1):0] out1;
+  wire [(`DATAWIDTH-1):0] out2;
+
+  reg [(`CODEBAG_SIZE_BITS-1):0]   counter;
+  reg [(`BRAM_ADDR_WIDTH-1):0]     cursor;
+  initial cursor = 0;
+  initial counter = 0;
+
+  reg                              write_flag;
+  reg                              dispatching_cbd;
+  initial write_flag = 0;
+  initial dispatching_cbd = 0;
 
   wire [(`BRAM_ADDR_WIDTH-1):0]   addr1;
-  wire [(`BRAM_ADDR_WIDTH-1):0]   addr2;
-  wire [(`BRAM_DATA_WIDTH-1):0]   val2;
   assign addr1 = write_flag ? inAddrWrite_d[(`DATAWIDTH-1):0] : inAddrRead_d[(`DATAWIDTH-1):0];
-  assign addr2 = (inCBD_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)])+cursor;
+  bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2);
 
-  bram14 mybram(clk, rst, write_flag, addr1, addr2, inDataWrite_d, out_d_, val2);
+  assign out_d_ = dispatching_cbd ? out2 : out1;
 
   always @(posedge clk) begin
 
@@ -161,39 +166,48 @@ sequence guarantee problem mentioned in the previous paragraph.
 
     if (!rst) begin
       `reset
-      cursor <= 0;
+      cursor  <= 0;
+      counter <= 0;
+      write_flag <= 0;
+      dispatching_cbd <= 0;
     end else begin
       write_flag <= 0;
 
-      if (!inAddrRead_r  && inAddrRead_a)  inAddrRead_a    <= 0;
+      if (!inAddrRead_r  && inAddrRead_a)  inAddrRead_a  <= 0;
       if (!inDataWrite_r && inDataWrite_a) inDataWrite_a <= 0;
       if (!inAddrWrite_r && inAddrWrite_a) inAddrWrite_a <= 0;
-
-      if ( out_r && !out_a) begin
-      end else if ( out_r &&  out_a) begin out_r <= 0;
-      end else if (!out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin
+      if (!inCBD_r &&  inCBD_a)            inCBD_a <= 0;
+
+      // assumes we never want a zero-length codebag
+      if ( inCBD_r && !inCBD_a && !out_r && !out_a) begin
+        if (!dispatching_cbd) begin
+          cursor          <= inCBD_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
+          counter         <= 0;
+          dispatching_cbd <= 1;
+        end
+        out_r <= 1;
+      end else if (inCBD_r && out_r &&  out_a) begin
+        out_r    <= 0;
+        if (counter != inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
+          cursor  <= cursor + 1;
+          counter <= counter + 1;
+        end else begin
+          inCBD_a <= 1;
+          counter <= 0;
+          dispatching_cbd <= 0;
+        end
+      end else if (!dispatching_cbd && out_r &&  out_a) begin out_r <= 0;
+      end else if (!dispatching_cbd && !out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin
         inAddrRead_a    <= 1;
         out_r           <= 1;
   
-      end else if (!out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin
+      end else if (!dispatching_cbd && !out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin
         // timing note: it's okay to set the *_a flags here because *_d will still
         // be valid on the *next* cycle, which is all we care about
         inAddrWrite_a   <= 1;
         inDataWrite_a   <= 1;
         out_r           <= 1;
         write_flag      <= 1;
-  
-      end else if ( outIhorn_r &&  outIhorn_a)                       begin outIhorn_r         <= 0;
-      end else if (!inCBD_r &&  inCBD_a) begin inCBD_a <= 0;
-      end else if ( inCBD_r && !inCBD_a && !outIhorn_r && !outIhorn_a) begin
-        if (cursor < inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
-          outIhorn_d    <= val2;
-          outIhorn_r    <= 1;
-          cursor        <= cursor + 1;
-        end else begin
-          inCBD_a       <= 1;
-          cursor        <= 0;
-        end
       end
     end
   end
@@ -214,6 +228,9 @@ sequence guarantee problem mentioned in the previous paragraph.
 // instructions not in any codebag are part of the "root codebag"
 // which is dispatched when the code is loaded
 
+memory.out:
+  [*] take, send;
+
 memory.inCBD:
   literal BOB;
   deliver;

diff --git a/src/edu/berkeley/fleet/assembler/Parser.java b/src/edu/berkeley/fleet/assembler/Parser.java
index 34688a3..fe59b8a 100644 (file)
--- a/src/edu/berkeley/fleet/assembler/Parser.java
+++ b/src/edu/berkeley/fleet/assembler/Parser.java
@@ -142,7 +142,8 @@ public class Parser {
                 inDataWrite = ship.getDock("inDataWrite");
                 inCBD = ship.getDock("inCBD");
                 out = ship.getDock("out");
-                ihorn = ship.getDock("outIhorn");
+                ihorn = out;
+                //ihorn = ship.getDock("outIhorn");
             }
             if ("Debug".equals(ship.getType()) && ship.getOrdinal()==0) {
                 debugIn = ship.getDock("in");

diff --git a/tests/codebags/fun-with-codebags.fleet b/tests/codebags/fun-with-codebags.fleet
index 4f82259..a116240 100644 (file)
--- a/tests/codebags/fun-with-codebags.fleet
+++ b/tests/codebags/fun-with-codebags.fleet
@@ -3,6 +3,9 @@
 #ship debug  : Debug
 #ship memory : Memory
 
+memory.out:
+ [*] take, send;
+
 memory.inCBD: literal {
     memory.inCBD: literal {
         memory.inCBD: literal {

diff --git a/tests/colliding-tokens.test b/tests/colliding-tokens.test
new file mode 100644 (file)
index 0000000..3c83b54
--- /dev/null
+++ b/tests/colliding-tokens.test
@@ -0,0 +1,19 @@
+#expect 2
+#expect 2
+#expect 2
+#expect 2
+
+#ship debug        : Debug
+#ship alu          : Alu2
+
+// attempts to get tokens to "collide" in the switch fabric
+
+debug.in:
+  literal 2;
+  [*] wait, deliver;
+
+alu.inOp: deliver; notify debug.in;
+alu.in1:  deliver; notify debug.in;
+alu.in2:  deliver; notify debug.in;
+alu.out:  collect; notify debug.in;
+

diff --git a/tests/memory/count.and.stride.fleet b/tests/memory/count.and.stride.fleet
index 93a2012..2d44135 100644 (file)
--- a/tests/memory/count.and.stride.fleet
+++ b/tests/memory/count.and.stride.fleet
@@ -15,8 +15,8 @@ debug.in:        [*] take, deliver;
 memory.inAddrRead:   [*] take, deliver;
 memory.inAddrWrite:   [*] take, deliver;
 memory.inDataWrite:   [*] take, deliver;
-memory.inCount:  [*] take, deliver;
-memory.inStride: [*] take, deliver;
+//memory.inCount:  [*] take, deliver;
+//memory.inStride: [*] take, deliver;
 fifo.in:         [*] take, deliver;
 
 // addresses and values to initialize the memory with