\usepackage{comment}
\usepackage{fancyhdr}
\usepackage{lastpage}
+\usepackage{multirow}
+\usepackage{multicol}
+\usepackage{rotating}
\include{megacz}
\bibliographystyle{alpha}
\pagestyle{fancyplain}
\begin{tabular}{rl}
\color{red}
-??-Mar
+29-Mar
+\color{black}
+& removed the {\tt L} flag (epilogues can now do this) \\
+& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
+& renamed {\tt data} instruction to {\tt literal} \\
+& renamed {\tt send} instruction to {\tt move} \\
+\color{red}
+23-Mar
\color{black}
& added ``if its predicate is true'' to repeat count \\
+& added note that red wires do not contact ships \\
+& changed name of {\tt flags} instruction to {\tt setFlags} \\
+& removed black dot from diagrams \\
+& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
+& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
+& indicated that only {\tt send} instructions which wait for data are torpedoable \\
+& added section ``Torpedo Details'' \\
+& removed {\tt torpedo} instruction \\
12-Mar
\color{black}
& renamed loop+repeat to outer+inner (not in red) \\
From a programmer's perspective, a token packet is indistinguishable
from a data packet with a unknown payload.
+\color{red}
+In the diagram below, the red wires carry instructions and the blue
+wires carry data; the switch fabric (gray area) carries both. Notice
+that the red (instruction) wires do not contact the ships. This is an
+advantage: ships are designed without any consideration for the
+instructions used to program their docks.
+\color{black}
+
\begin{center}
-\epsfig{file=overview,width=3in}\\
+\epsfig{file=overview,width=2.5in}\\
{\it Overview of a Fleet processor; gray shading represents a
packet-switched network fabric; blue lines carry data, red lines
carry instructions.}
\begin{bytefield}{37}
\bitheader[b]{0,10,11,36}\\
\color{black}
- \bitbox{1}{A}
- \bitbox{1}{OL}
+ \bitbox{1}{\color{red}I\color{black}}
+ \bitbox{1}{\color{red}OS\color{black}}
\bitbox{2}{P}
\color{light}
\bitbox[tbr]{22}{}
Collections of one or more micro instruction are known as {\it
composite instructions}.
-The {\tt A} bit stands for {\tt Armor}\footnote{this is to be
- pronounced with a Boston accent (``AAHH-mir'')}.
-The {\tt OL} bit indicates whether or not this instruction is part of
-an outer loop. Both of the preceding bits are explained in the next section.
+\color{red}
+The {\tt I} bit stands for {\tt Interruptible}\color{black}. The \color{red}{\tt OS}
+(``One Shot'')\color{black}\ bit indicates whether or not this instruction is part
+of an outer loop. Both of the preceding bits are explained in the
+next section.
\color{black}
Note the circle on the path between ``instr horn'' and ``instr fifo'';
this is known as ``the hatch''. The hatch has two states: sealed and
unsealed. When the machine powers up, the hatch is unsealed; it is
-sealed by the {\tt tail} instruction and unsealed as described below.
-
-When a non-{\tt torpedo} instruction arrives at the instruction horn,
-it waits there until the hatch is in the unsealed state. The
-instruction then enters the instruction fifo.
-
-When an instruction emerges from the instruction fifo, it arrives at
-the ``on deck'' stage and starts two processes {\it
- concurrently}:
-
-\begin{itemize}
-\item
-{\bf Process \#1}\\
-If the instruction has the {\tt OL} bit set and the value of {\tt OC}
-is nonzero, this process will wait for the hatch to be {\it sealed}
-and then enqueue a duplicate copy of the instruction into the instruction fifo.
-
-\item
-{\bf Process \#2}\\
-If the value of {\tt OC} is zero and the instruction at on-deck is
-{\it not} an {\tt setOuter} instruction whose {\tt OL} bit is cleared,
-this process will unseal the hatch, set the {\it inner} loop counter
-to zero, and terminate.
-
-Otherwise, the instruction will execute one or more times, as
-determined by the flags, predicate, and inner loop counter (see
-below). If the instruction's {\tt A}rmor bit is not
-set\footnote{note: we need to say something about only {\tt send}
- instructions being {\tt torpedo}able}, each execution attempt will
-be arbitrated against the arrival of a {\tt torpedo} instruction at
-the instruction horn. If the {\tt torpedo} wins, the {\it outer} loop
-counter is set to zero and this process terminates immediately.
-\end{itemize}
-
-When both processes have completed, the on deck stage is vacated and
-another instruction may enter it.
-
-Note that when a {\tt torpedo} arrives at the instruction horn it will
-wait there until on deck is occupied by an instruction whose {\tt
- A}rmor bit is {\it not set}, but it does {\it not} wait for the
-hatch to be unsealed.
-
-\color{black}
-
-\subsection{Inner and Outer Loops}
-
-
-
-Using the mechanisms described above, a programmer can perform two
-types of loops: {\it inner} loops of only one instruction and {\it
- outer} loops of multiple instructions. Inner loops may be nested
-within an outer loop, but no other nesting of loops is allowed. The
-paths used by inner loops and outer loops are shown below:
+sealed by the {\tt tail} instruction and unsealed \color{red}whenever
+the outer loop counter is set to zero (for any
+reason\footnote{\color{red}this includes {\tt OLC} being decremented
+ to zero, a {\tt setOuter} with a literal field of zero, a {\tt
+ setOuter} which copies a zero from the data register to {\tt OLC},
+ or the occurrence of a torpedo\color{black}}).\color{black}
+
+When an instruction arrives at the instruction horn, it waits there
+until the hatch is in the unsealed state. The instruction then enters
+the instruction fifo. When an instruction emerges from the
+instruction fifo, it arrives at the ``on deck'' stage, where it may
+execute.
+
+\subsubsection{Inner and Outer Loops}
+
+A programmer can perform two types of loops: {\it inner} loops of only
+one micro-instruction and {\it outer} loops of multiple
+micro-instructions. Inner loops may be nested within an outer loop,
+but no other nesting of loops is allowed. The paths used by inner
+loops and outer loops are shown below:
\begin{center}
\begin{minipage}{2in}
\end{minipage}
\end{center}
-Each type of loop has a counter associated with it: the {\tt IC}
-counter for inner loops and the {\tt OC} counter for outer loops. The
-inner loop counter applies only to {\tt send} instructions; all other
-instructions ignore the inner loop counter. When a {\tt send}
-instruction reaches the on deck position,
\color{red}
-if its predicate is true
-\color{black}
-it
-will execute at least once; the number of times it executes after that
-is determined by the inner loop counter.
+
+Each type of loop has a counter associated with it: the {\tt ILC}
+counter for inner loops and the {\tt OLC} counter for outer loops.
+The inner loop counter applies only to certain ``inner-looping''
+instructions (see the table below for details). When such an
+instruction reaches On Deck, if its predicate is true it will execute
+a number of times equal to {\tt ILC+1}, and leave {\tt ILC=0} after
+executing. Non-inner-looping instructions and instructions whose
+predicate is false do not decrement {\tt ILC}.
The outer loop counter applies to all instructions {\it except} the
-instruction {\tt setOuter} with {\tt OL=0}, because such instructions
+instruction {\tt setOuter} with {\tt OS=1}, because such instructions
are needed to reset the outer loop counter after it becomes zero.
-However, {\tt setOuter} with {\tt OL} set to {\it one} is useful for
+However, predicated {\tt setOuter} with {\tt OS=0} is useful for
resetting the loop counter in the middle of the execution of a loop.
\color{black}
+\subsubsection{On Deck}
+\color{red} The
+table below lists the actions which may be taken when an
+instruction arrives on deck:
+
+\begin{center}
+\def\side#1{\begin{sideways}\parbox{15mm}{#1}\end{sideways}}
+\begin{tabular}{|r|ccccc|cccccc|}\hline
+%&\multicolumn{10}{c}{Predicate}&\\
+%&\multicolumn{10}{c}{True}&\\\hline
+&\multicolumn{5}{c}{Outer-Looping} &\multicolumn{5}{c}{One-Shot}&\\
+&\multicolumn{5}{c}{{\tt (OS=0)}} &\multicolumn{5}{c}{{\tt (OS=1)}}&\\
+&\side{{\tt move}}
+&\side{{\tt literal}}
+&\side{{\tt setFlags}}
+&\side{{\tt setInner}}
+&\side{{\tt setOuter}}
+&\side{{\tt move}}
+&\side{{\tt literal}}
+&\side{{\tt setFlags}}
+&\side{{\tt setInner}}
+&\side{{\tt setOuter}}
+&
+\\\hline
+Wait for hatch sealed & + & + & + & + & + & & & & & & \\
+Fill IF0 w/ copy of self & + & + & + & + & + & & & & & & \\\hline
+Request arbiter & P+$\star$ & & & & & P+$\star$ & & & & & \\
+Potentially torpedoable & P+$\star$ & & & & & P+$\star$ & & & & & \\\hline
+Execute & P+ & P+& P+& P+& P+ & ? & ? & ? & ? & P & \\
+Inner-looping & P+ & & & & ? & P+ & & & & ? & \\
+\hline
+\end{tabular}
+
+\begin{tabular}{|r|l|}\hline
++ & Only if {\tt OLC>0} (ie {\tt OLC} is positive) \\
+P & Only if predicate is true \\
+P+ & Only if predicate is true and {\tt OLC>0} \\
+P+$\star$ & Only if predicate is true and {\tt OLC>0} and {\tt I=1} and one of {\tt Ti},{\tt Di},{\tt Do} true. \\
+? & to discuss \\\hline
+\end{tabular}
+\end{center}
+
+\subsubsection{\color{red}Torpedo\color{black}}
+
+\color{red}
+There is a small fifo (not shown) before the latch marked
+``Instruction Horn''; after the {\tt tail} instruction seals the
+hatch, any subsequent instructions will queue up in this fifo until
+the hatch is unsealed. This is typically used as storage for a ``loop
+epilogue'' -- a sequence of instructions to be executed after a
+torpedo arrives or the outer loop counter expires.
+
+Each dock has a fourth connection to the switch fabric (not shown),
+called its {\it torpedo destination}. Anything (even a token) sent to
+this destination is treated as a torpedo. Note that because this is a
+distinct destination, instructions or data queued up in the other
+destination fifos will not prevent a torpedo from occuring.
+
+When a data item or token arrives at the torpedo destination, it lies
+there in wait until On Deck holds a potentially torpedoable
+instruction (see previous table). Once this is the case, the torpedo
+causes the inner and outer loop counters to be set to zero (and
+therefore also unseals the hatch).\footnote{it is unspecified whether
+ the torpedoed instruction is requeued or not; this may or may not
+ occur, nondeterministically. It is the programmer's responsibility
+ to ensure that the program behaves the same whether this happens or
+ not. We think that this will not matter in most situations.}
+
+\color{black}
+
+
\subsection{Flags}
-The pump has four flags: {\tt A}, {\tt B}, {\tt L}, and {\tt S}. Of
-these four, only the first two may be modified directly by
-instructions.
+The pump has \color{red}three\color{black}\ flags: {\tt A}, {\tt B},
+and {\tt S}.
\begin{itemize}
\item The {\tt A} and {\tt B} flags are general-purpose flags which
may be set and cleared by the programmer.
-\item
-
- The {\tt L} flag, known as the {\it last} flag, is set whenever
- the value in the outer counter ({\tt OC}) is one,
+%\item
+%
+% The {\tt L} flag, known as the {\it last} flag, is set whenever
+% the value in the outer counter ({\tt OLC}) is one,
\color{black}
- indicating
- that the dock is in the midst of the last iteration of an
- outer loop. This flag can be used to perform certain
- operations (such as sending a completion token) only on the last
- iteration of an outer loop.
+% indicating
+% that the dock is in the midst of the last iteration of an
+% outer loop. This flag can be used to perform certain
+% operations (such as sending a completion token) only on the last
+% iteration of an outer loop.
\item The {\tt S} flag, known as the {\it summary} flag. Its value is
determined by the ship, but unless stated otherwise, it should
\begin{itemize}
\item {\tt 00:} if {\tt A} is set
\item {\tt 10:} if {\tt B} is set
-\item {\tt 01:} if {\tt L} is set ({\tt OC=1})
+\item {\tt 01:} \color{red}TBD\color{black}
\item {\tt 11:} always
\end{itemize}
\pagebreak
-\subsection{{\tt send} (variants: {\tt sendto}, {\tt dispatch})}
+\section{Instructions}
+
+\color{red}
+
+Here is a list of the instructions supported by the dock:
+
+\begin{center}
+\begin{tabular}{|l|}\hline
+{\tt move} (variants: {\tt moveto}, {\tt dispatch}) \\
+{\tt literal} (variants: {\tt literalhi}, {\tt literallo})\\
+{\tt setFlags} \\
+{\tt setInner} \\
+{\tt setOuter} \\
+%{\tt torpedo} \\
+{\tt tail} \\\hline
+\end{tabular}
+\end{center}
+
+{\tt tail} {\it will probably become a bit on every instruction rather than
+ its own instruction}
+
+\color{black}
+
+
+\subsection{{\tt move} (variants: {\tt moveto}, {\tt dispatch})}
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
\bitheader[b]{12-16,19,21}\\
\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
+ \bitbox{1}{I}
+ \bitbox{1}{OS}
\bitbox{2}{P}
\color{black}
\bitbox{3}{001}
\begin{bytefield}{26}
\bitheader[b]{0,10,11}\\
- \bitbox[1]{13}{\raggedleft {\tt sendto} ({\tt LiteralPath\to Path})}
+ \bitbox[1]{13}{\raggedleft {\tt moveto} ({\tt LiteralPath\to Path})}
\bitbox[r]{1}{}
\bitbox{1}{\tt 1}
\bitbox{11}{\tt LiteralPath}
\begin{bytefield}{26}
\bitheader[b]{10,11}\\
- \bitbox[1]{13}{\raggedleft {\tt send} ({\tt Path} unchanged):}
+ \bitbox[1]{13}{\raggedleft {\tt move} ({\tt Path} unchanged):}
\bitbox[r]{1}{}
\bitbox{1}{\tt 0}
\bitbox{1}{\tt 0}
\end{itemize}
The data successor and token successor must both be empty in order for
-a {\tt send} instruction to attempt execution.
+a {\tt move} instruction to attempt execution.
The inner loop counter can hold a number {\tt 0..MAX} or a special
-value $\infty$. If {\tt IC} is nonzero after execution of a {\tt
- send} instruction, the instruction will execute again, and {\tt IC}
-will be latched with {\tt (IC==$\infty$?$\infty$:max(IC-1, 0))}. When
+value $\infty$. If {\tt ILC} is nonzero after execution of a {\tt
+ move} instruction, the instruction will execute again, and {\tt ILC}
+will be latched with {\tt (ILC==$\infty$?$\infty$:max(ILC-1, 0))}. When
the inner loop counter reaches zero, the instruction ceases executing.
\pagebreak
-\subsection{{\tt data}, {\tt datahi}, {\tt datalo}}
+\subsection{{\tt literal}, {\tt literalhi}, {\tt literallo}}
These instructions load part or all of the data latch ({\tt D}).
-{\tt datahi: Literal[18:1]\to D[37:20]} (and {\tt Literal[18]\to S})
+{\tt literalhi: Literal[18:1]\to D[37:20]} (and {\tt Literal[18]\to S})
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
\bitheader[b]{0,18,19,21}\\
\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
+ \bitbox{1}{I}
+ \bitbox{1}{OS}
\bitbox{2}{P}
\color{black}
\bitbox{1}{0}
\bitbox{18}{Literal}
\end{bytefield}}
-{\tt datalo: Literal[19:1]\to D[19:1]}
+{\tt literallo: Literal[19:1]\to D[19:1]}
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
\bitheader[b]{0,18,19,21}\\
\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
+ \bitbox{1}{I}
+ \bitbox{1}{OS}
\bitbox{2}{P}
\color{black}
\bitbox{1}{0}
\bitbox{19}{Literal}
\end{bytefield}}
-{\tt data:}
+{\tt literal:}
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
\bitheader[b]{0,18,19,21}\\
\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
+ \bitbox{1}{I}
+ \bitbox{1}{OS}
\bitbox{2}{P}
\color{black}
\bitbox{1}{1}
-\subsection{{\tt flags}}
+\subsection{
+\color{red}
+{\tt setFlags}
+\color{black}
+}
\setlength{\bitwidth}{5mm}
{\tt
\begin{bytefield}{26}
\bitheader[b]{0,7,8,15,16-19,21}\\
\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
+ \bitbox{1}{I}
+ \bitbox{1}{OS}
\bitbox{2}{P}
\color{black}
\bitbox{3}{000}
\bitbox{1}{0}
- \bitbox{2}{00}
+\color{red}
+ \bitbox{6}{nextA}
+ \bitbox{6}{nextB}
+ \bitbox{6}{nextS}
\color{black}
- \bitbox{8}{nextA}
- \bitbox{8}{nextB}
\end{bytefield}}
The {\tt P} field is a predicate; if it does not hold, the instruction
-is ignored. Otherwise the two flags ({\tt A} and {\tt B}) are updated
-according to the {\tt nextA} and {\tt nextB} fields; each specifies
-the new value as the logical {\tt OR} of zero or more inputs:
+is ignored. Otherwise the flags are updated according to the {\tt
+ nextA}, {\tt nextB}, and {\tt nextS} fields; each specifies the new
+value as the logical {\tt OR} of zero or more inputs:
\begin{center}
{\tt
-\begin{bytefield}{8}
- \bitheader[b]{0-7}\\
+\begin{bytefield}{6}
+ \bitheader[b]{0-5}\\
\bitbox{1}{${\text{\tt A}}$}
\bitbox{1}{$\overline{\text{\tt A}}$}
\bitbox{1}{${\text{\tt B}}$}
\bitbox{1}{$\overline{\text{\tt B}}$}
\bitbox{1}{${\text{\tt S}}$}
\bitbox{1}{$\overline{\text{\tt S}}$}
- \bitbox{1}{${\text{\tt L}}$}
- \bitbox{1}{$\overline{\text{\tt L}}$}
\end{bytefield}}
\end{center}
\begin{bytefield}{26}
\bitheader[b]{16-19,21}\\
\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
+ \bitbox{1}{I}
+ \bitbox{1}{OS}
\bitbox{2}{P}
\color{black}
\bitbox{3}{000}
- \bitbox{1}{0}
+ \bitbox{1}{1}
\bitbox{2}{01}
\color{light}
\bitbox[tbr]{8}{}
\subsection{{\tt setOuter}}
-This instruction loads the outer loop counter {\tt OC} with either
-{\tt max(0,OC-1)}, a literal or the contents of the {\tt data}
+This instruction loads the outer loop counter {\tt OLC} with either
+{\tt max(0,OLC-1)}, a literal or the contents of the {\tt data}
register.
\setlength{\bitwidth}{5mm}
\begin{bytefield}{26}
\bitheader[b]{16-19,21,24}\\
\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
+ \bitbox{1}{I}
+ \bitbox{1}{OS}
\color{light}
\bitbox[tbr]{2}{P}
\color{black}
\bitbox{3}{000}
- \bitbox{1}{0}
+ \bitbox{1}{1}
\bitbox{2}{10}
\color{light}
\bitbox[tbr]{9}{}
\end{bytefield}}\\
\begin{bytefield}{26}
- \bitbox[r]{19}{\raggedleft {\tt max(0,OC-1)}:\hspace{0.2cm}\ }
+ \bitbox[r]{19}{\raggedleft {\tt max(0,OLC-1)}:\hspace{0.2cm}\ }
\bitbox{2}{\tt 00}
%\color{light}
\bitbox[tbr]{5}{}
\bitbox{6}{\tt Literal}
\end{bytefield}
-\pagebreak
-\subsection{{\tt takeOuterLoopCounter}}
-
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{16-19,21}\\
-\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
- \bitbox{2}{P}
-\color{black}
- \bitbox{3}{000}
- \bitbox{1}{0}
- \bitbox{2}{11}
-\color{light}
- \bitbox[tbr]{16}{}
-\color{black}
-\end{bytefield}}
-
-This instruction copies the value in the outer loop counter {\tt OC}
-into the least significant bits of the data latch and leaves all other
-bits of the data latch unchanged.
-
-\subsection{{\tt takeInnerLoopCounter}}
-
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{16-19,21}\\
-\color{light}
- \bitbox{1}{A}
- \bitbox{1}{OL}
- \bitbox{2}{P}
-\color{black}
- \bitbox{3}{???}
- \bitbox{1}{?}
- \bitbox{2}{??}
-\color{light}
- \bitbox[tbr]{16}{}
-\color{black}
-\end{bytefield}}
-
-This instruction copies the value in the inner loop counter {\tt IC}
-into the least significant bits of the data latch and leaves all other
-bits of the data latch unchanged.
+%\subsection{{\tt torpedo}}
+%
+%\setlength{\bitwidth}{5mm}
+%{\tt
+%\begin{bytefield}{26}
+% \bitheader[b]{0,5,16-19,21}\\
+%\color{light}
+% \bitbox{4}{}
+%\color{black}
+% \bitbox{3}{000}
+% \bitbox{1}{1}
+% \bitbox{2}{00}
+%\color{light}
+% \bitbox[tbr]{16}{}
+%\end{bytefield}}
+%
+%
+%When a {\tt torpedo} instruction reaches the instruction horn, it will
+%wait there until an instruction is on deck whose {\tt A}rmor bit is
+%not set. The {\tt torpedo} will then cause ``Process \#2'' of the on
+%deck instruction to terminate and will set the outer loop counter to zero.
-\subsection{{\tt torpedo}}
+\subsection{{\tt tail}}
-\setlength{\bitwidth}{5mm}
-{\tt
-\begin{bytefield}{26}
- \bitheader[b]{0,5,16-19,21}\\
-\color{light}
- \bitbox{4}{}
+\color{red}
+{\it This will probably become a bit on every instruction rather than
+ its own instruction. The only problem is that we have run out of bits in the {\tt literal} instruction. Two possible solutions: (a) declare that {\tt literal} cannot be the last instruction in a loop or (b) because {\tt literal} instructions cannot be torpedoed anyways, re-use its {\tt I} bit for this purpose.}
\color{black}
- \bitbox{3}{000}
- \bitbox{1}{1}
- \bitbox{2}{00}
-\color{light}
- \bitbox[tbr]{16}{}
-\end{bytefield}}
-
-
-When a {\tt torpedo} instruction reaches the instruction horn, it will
-wait there until an instruction is on deck whose {\tt A}rmor bit is
-not set. The {\tt torpedo} will then cause ``Process \#2'' of the on
-deck instruction to terminate and will set the outer loop counter to zero.
-
-\subsection{{\tt tail}}
\setlength{\bitwidth}{5mm}
{\tt
The {\tt tail} instruction does not enter the instruction fifo.
\color{black}
-
-
%\pagebreak
-%\subsection{{\tt interrupt}}
+%\subsection{{\tt takeOuterLoopCounter}}
%
%\setlength{\bitwidth}{5mm}
%{\tt
%\begin{bytefield}{26}
+% \bitheader[b]{16-19,21}\\
+%\color{light}
+% \bitbox{1}{A}
+% \bitbox{1}{OS}
+% \bitbox{2}{P}
+%\color{black}
+% \bitbox{3}{000}
+% \bitbox{1}{0}
+% \bitbox{2}{11}
+%\color{light}
+% \bitbox[tbr]{16}{}
+%\color{black}
+%\end{bytefield}}
+%
+%This instruction copies the value in the outer loop counter {\tt OLC}
+%into the least significant bits of the data latch and leaves all other
+%bits of the data latch unchanged.
+%
+%\subsection{{\tt takeInnerLoopCounter}}
+%
+%\setlength{\bitwidth}{5mm}
+%{\tt
+%\begin{bytefield}{26}
+% \bitheader[b]{16-19,21}\\
+%\color{light}
+% \bitbox{1}{A}
+% \bitbox{1}{OS}
+% \bitbox{2}{P}
+%\color{black}
+% \bitbox{3}{???}
+% \bitbox{1}{?}
+% \bitbox{2}{??}
+%\color{light}
+% \bitbox[tbr]{16}{}
+%\color{black}
+%\end{bytefield}}
+%
+%This instruction copies the value in the inner loop counter {\tt ILC}
+%into the least significant bits of the data latch and leaves all other
+%bits of the data latch unchanged.
+%
+%
+%
+%%\pagebreak
+%%\subsection{{\tt interrupt}}
+%%
+%%\setlength{\bitwidth}{5mm}
+%{\tt
+%\begin{bytefield}{26}
% \bitheader[b]{0,5,16-19,21}\\
%\color{light}
% \bitbox{4}{}
projects / fleet.git / commitdiff
