use different filename for main.ace to work around xilinx bug

diff --git a/Makefile b/Makefile
index c0932db..c5a2d7d 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -90,7 +90,8 @@ synth:
        $(xilinx_ise)par -w -intstyle xflow -t 99 -pl std -rl std main_map.ncd main.ncd main.pcf
        $(xilinx_ise)bitgen -intstyle xflow -d -f main.ut main.ncd
 #      $(xilinx_ise)trce -intstyle xflow -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
-       $(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ml410 -ace main.ace
+       $(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ml410 -ace mainx.ace
+       mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
 
 
 runserver: fleet.jar