cleanup Alu1 and Alu2 FPGA code

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index 1ac349d..524fb8e 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -49,44 +49,26 @@ The result of this operation is then made available at {\tt out}.
 
 == FleetSim ==============================================================
 == FPGA ==============================================================
-  reg                       have_a;
-  reg [(`PACKET_WIDTH-1):0] reg_a;
-  reg                       have_op;
-  reg [(`PACKET_WIDTH-1):0] reg_op;
-  reg [(`PACKET_WIDTH-1):0] extrabits;
 
   always @(posedge clk) begin
     if (!rst) begin
-      have_a = 0;
-      have_op = 0;
       `reset
     end else begin
-    if (!have_a) begin
-      `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
+      if (out_r    && out_a)    out_r    <= 0;
+      if (!in_r    && in_a)     in_a     <= 0;
+      if (!inOp_r  && inOp_a)   inOp_a   <= 0;
+      if (!out_r && !out_a && in_r && !in_a && inOp_r && !inOp_a) begin
+        out_r <= 1;
+        in_a <= 1;
+        inOp_a <= 1;
+        case (inOp_d)
+          0: out_d <= -in_d;
+          1: out_d <= in_d+1;
+          2: out_d <= in_d-1;
+          3: out_d <= (in_d<0) ? (-in_d) : in_d;
+          default: out_d <= 0;
+        endcase        
       end
-    if (!have_op) begin
-      `onread(inOp_r, inOp_a)
-         have_op   = 1;
-         reg_op    = inOp_d[(`DATAWIDTH-1):0];
-         extrabits = inOp_d[(`PACKET_WIDTH-1):`DATAWIDTH];
-      end
-    end
-  
-    if (have_a && have_op) begin
-      case (reg_op)
-        0: out_d = -reg_a;
-        1: out_d = reg_a+1;
-        2: out_d = reg_a-1;
-        3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
-        4: out_d = 37'b1111111111111111111111111111111111111;
-        5: out_d = extrabits;
-        default: out_d = 0;
-      endcase        
-      `onwrite(out_r, out_a)
-        have_a  = 0;
-        have_op = 0;
-      end
-    end
     end
   end
 
@@ -101,19 +83,31 @@ The result of this operation is then made available at {\tt out}.
 
 #ship debug        : Debug
 #ship alu1         : Alu1
+#ship fifo         : Fifo
+
+debug.in:
+  [*] take, deliver;
 
-debug.in:   [*] take, deliver;
 alu1.in:
   literal 9;
-  load repeat counter with 4; deliver;
+  load repeat counter with 4;
+  deliver;
   take, deliver;
 
 alu1.out:
-  load repeat counter with 4; take, sendto debug.in;
+  load repeat counter with 4;
+  take, sendto debug.in;
   sendto alu1.in;
   take, sendto debug.in;
 
 alu1.inOp:
+  notify fifo.out;
+  [*] take, deliver, notify fifo.out;
+
+fifo.out:
+  [*] wait, take, sendto alu1.inOp;
+
+fifo.in:
    literal 1; deliver;
    literal 2; deliver;
    literal 3; deliver;

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index fd8a33f..1a17432 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -74,46 +74,29 @@ public void service() {
 
 == FPGA ==============================================================
 
-  reg                    have_a;
-  reg [(`DATAWIDTH-1):0] reg_a;
-  reg                    have_b;
-  reg [(`DATAWIDTH-1):0] reg_b;
-  reg                    have_op;
-  reg [(`DATAWIDTH-1):0] reg_op;
-
   always @(posedge clk) begin
     if (!rst) begin
-      have_a = 0;
-      have_b = 0;
-      have_op = 0;
       `reset
     end else begin
-    if (!have_a) begin
-      `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
-      end
-    if (!have_b) begin
-      `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
-      end
-    if (!have_op) begin
-      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
-      end
-  
-    if (have_a && have_b && have_op) begin
-      case (reg_op)
-        0: out_d = reg_a + reg_b;
-        1: out_d = reg_a - reg_b;
-        2: out_d = reg_a > reg_b ? reg_a : reg_b;
-        3: out_d = reg_a > reg_b ? reg_b : reg_a;
-        default: out_d = 0;
-      endcase        
-      `onwrite(out_r, out_a)
-        have_a  = 0;
-        have_b  = 0;
-        have_op = 0;
+      if (out_r    && out_a)    out_r    <= 0;
+      if (!in1_r   && in1_a)    in1_a    <= 0;
+      if (!in2_r   && in2_a)    in2_a    <= 0;
+      if (!inOp_r  && inOp_a)   inOp_a   <= 0;
+      if (!out_r && !out_a && in1_r && !in1_a && in2_r && !in2_a && inOp_r && !inOp_a) begin
+        out_r <= 1;
+        in1_a <= 1;
+        in2_a <= 1;
+        inOp_a <= 1;
+        case (inOp_d)
+          0: out_d <= in1_d + in2_d;
+          1: out_d <= in1_d - in2_d;
+          2: out_d <= in1_d > in2_d ? in1_d : in2_d;
+          3: out_d <= in1_d > in2_d ? in2_d : in1_d;
+          default: out_d <= 0;
+        endcase        
       end
     end
   end
-  end
 
 == Test ==============================================================================
 // expected output