fixed memory ship, fpga implementation now works

diff --git a/ships/Memory.ship b/ships/Memory.ship
index 326db60..ae99d10 100644 (file)
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -2,11 +2,9 @@ ship: Memory
 
 == Ports ===========================================================
 data  in:    inCBD
-data  in:    inAddr.read
-data  in:    inAddr.write
-data  in:    inAddr.readMany
-data  in:    inAddr.writeMany
-data  in:    inData
+data  in:    inAddrRead
+data  in:    inAddrWrite
+data  in:    inDataWrite
 data  in:    inStride
 data  in:    inCount
 
@@ -64,8 +62,8 @@ data  out:   out
             dispatch((int)addr, (int)size);
         }
         if (count > 0 && writing) {
-            if (box_inData.dataReadyForShip() && box_out.readyForDataFromShip()) {
-               writeMem((int)addr, box_inData.removeDataForShip());
+            if (box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
+               writeMem((int)addr, box_inDataWrite.removeDataForShip());
                box_out.addDataFromShip(0);
                count--;
                addr += stride;
@@ -78,25 +76,25 @@ data  out:   out
                addr += stride;
             }
 
-        } else if (box_inAddr.dataReadyForShip() && box_out.readyForDataFromShip()) {
-            Packet packet = box_inAddr.peekPacketForShip();
+        } else if (box_inAddrRead.dataReadyForShip() && box_out.readyForDataFromShip()) {
+            Packet packet = box_inAddrRead.peekPacketForShip();
             if (packet.destination.getDestinationName().equals("read")) {
-                box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
-            } else if (packet.destination.getDestinationName().equals("write") && box_inData.dataReadyForShip()) {
-                writeMem((int)box_inAddr.removeDataForShip(),
-                         box_inData.removeDataForShip());
+                box_out.addDataFromShip(readMem((int)box_inAddrRead.removeDataForShip()));
+            } else if (packet.destination.getDestinationName().equals("write") && box_inDataWrite.dataReadyForShip()) {
+                writeMem((int)box_inAddrRead.removeDataForShip(),
+                         box_inDataWrite.removeDataForShip());
                 box_out.addDataFromShip(0);
             } else if (packet.destination.getDestinationName().equals("writeMany")
                        && box_inStride.dataReadyForShip()
                        && box_inCount.dataReadyForShip()) {
-                addr = box_inAddr.removeDataForShip();
+                addr = box_inAddrRead.removeDataForShip();
                 stride = box_inStride.removeDataForShip();
                 count = box_inCount.removeDataForShip();
                 writing = true;
             } else if (packet.destination.getDestinationName().equals("readMany")
                        && box_inStride.dataReadyForShip()
                        && box_inCount.dataReadyForShip()) {
-                addr = box_inAddr.removeDataForShip();
+                addr = box_inAddrRead.removeDataForShip();
                 stride = box_inStride.removeDataForShip();
                 count = box_inCount.removeDataForShip();
                 writing = false;
@@ -138,6 +136,7 @@ endmodule
 module memory (clk, 
                cbd_r,          cbd_a_,         cbd_d,
                in_addr_r,      in_addr_a_,     in_addr_d,
+               write_addr_r,   write_addr_a_,  write_addr_d,
                write_data_r,   write_data_a_,  write_data_d,
                stride_r,       stride_a_,      stride_d,
                count_r,        count_a_,       count_d,
@@ -149,6 +148,7 @@ module memory (clk,
 
   input  clk;
   `input(in_addr_r,      in_addr_a,     in_addr_a_,     [(2+`DATAWIDTH-1):0],       in_addr_d)
+  `input(write_addr_r,   write_addr_a,  write_addr_a_,  [(2+`DATAWIDTH-1):0],       write_addr_d)
   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
   `input(stride_r,       stride_a,      stride_a_,      [(`DATAWIDTH-1):0],         stride_d)
   `input(count_r,        count_a,       count_a_,       [(`DATAWIDTH-1):0],         count_d)
@@ -208,6 +208,7 @@ module memory (clk,
 
     if (!in_addr_r && in_addr_a) in_addr_a = 0;
     if (!write_data_r && write_data_a) write_data_a = 0;
+    if (!write_addr_r && write_addr_a) write_addr_a = 0;
 
     if (command_valid_read) begin
       command_valid_read  <= 0;
@@ -223,17 +224,17 @@ module memory (clk,
         send_read <= 0;
       end
 
-    end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
+    end else if (in_addr_r) begin
       in_addr_a                        = 1;
       send_read                       <= 1;
       current_instruction_read_from   <= in_addr_d[(`DATAWIDTH-1):0];
 
-    end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
-      in_addr_a          = 1;
+    end else if (write_addr_r && write_data_r) begin
+      write_addr_a       = 1;
       write_data_a       = 1;
       send_done         <= 1;
       write_flag        <= 1;
-      in_addr           <= in_addr_d[(`DATAWIDTH-1):0];
+      in_addr           <= write_addr_d[(`DATAWIDTH-1):0];
       write_data        <= write_data_d;
 
     end else if (ihorn_full && launched) begin

diff --git a/tests/memory/count.and.stride.fleet b/tests/memory/count.and.stride.fleet
index 505f9c2..e56402a 100644 (file)
--- a/tests/memory/count.and.stride.fleet
+++ b/tests/memory/count.and.stride.fleet
@@ -12,20 +12,21 @@
 
 // dumb configurations
 debug.in:        [*] take, deliver;
-memory.inAddr:   [*] take, deliver;
-memory.inData:   [*] take, deliver;
+memory.inAddrRead:   [*] take, deliver;
+memory.inAddrWrite:   [*] take, deliver;
+memory.inDataWrite:   [*] take, deliver;
 memory.inCount:  [*] take, deliver;
 memory.inStride: [*] take, deliver;
 fifo.in:         [*] take, deliver;
 
 // addresses and values to initialize the memory with
-1:  sendto memory.inAddr.writeMany;
+1:  sendto memory.inAddrWrite;
 4:  sendto memory.inCount;
 1:  sendto memory.inStride;
-11: sendto memory.inData;
-12: sendto memory.inData;
-13: sendto memory.inData;
-14: sendto memory.inData;
+11: sendto memory.inDataWrite;
+12: sendto memory.inDataWrite;
+13: sendto memory.inDataWrite;
+14: sendto memory.inDataWrite;
 
 // send write-completion tokens to the fifo output
 memory.out:
@@ -36,7 +37,7 @@ memory.out:
 // the read addresses
 fifo.out:
   [4] wait;
-  take, sendto memory.inAddr.readMany;
+  take, sendto memory.inAddrRead;
 
 // read addresses
 4: sendto fifo.in;

diff --git a/tests/memory/memory-test.fleet b/tests/memory/memory-test.fleet
index 16d4d4b..747e5ae 100644 (file)
--- a/tests/memory/memory-test.fleet
+++ b/tests/memory/memory-test.fleet
@@ -1,5 +1,4 @@
 // output ///////////////////////////////////////////////////////////////////
-#skip
 #expect 14
 #expect 13
 #expect 12
@@ -11,31 +10,32 @@
 #ship fifo         : Fifo
 
 // dumb configurations
-debug.in:        [*] take, deliver;
-memory.inAddr:   [*] take, deliver;
-memory.inData:   [*] take, deliver;
-fifo.in:         [*] take, deliver;
-
-// addresses and values to initialize the memory with
-1:  sendto memory.inAddr.write;
-2:  sendto memory.inAddr.write;
-3:  sendto memory.inAddr.write;
-4:  sendto memory.inAddr.write;
-11: sendto memory.inData;
-12: sendto memory.inData;
-13: sendto memory.inData;
-14: sendto memory.inData;
+debug.in:           [*] take, deliver;
+memory.inAddrRead:  [*] take, deliver;
+memory.inAddrWrite: [*] take, deliver;
+memory.inDataWrite: [*] take, deliver;
+fifo.in:            [*] take, deliver;
 
 // send write-completion tokens to the fifo output
 memory.out:
   [4] take, notify fifo.out;
   [*] take, sendto debug.in;
 
+// addresses and values to initialize the memory with
+1:  sendto memory.inAddrWrite;
+2:  sendto memory.inAddrWrite;
+3:  sendto memory.inAddrWrite;
+4:  sendto memory.inAddrWrite;
+11: sendto memory.inDataWrite;
+12: sendto memory.inDataWrite;
+13: sendto memory.inDataWrite;
+14: sendto memory.inDataWrite;
+
 // when the write-completion tokens accumulate, unleash
 // the read addresses
 fifo.out:
   [4] wait;
-  [4] take, sendto memory.inAddr.read;
+  [4] take, sendto memory.inAddrRead;
 
 // read addresses
 4:  sendto fifo.in;