minor updates to ZBT ship

diff --git a/Makefile b/Makefile
index f4b0cdd..62b7983 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -356,7 +356,7 @@ runtest: fleet.jar
        cp lib/suncvs.jar suncvs/marina/testCode/MarinaTest.jar
        ssh ${sun_server} 'skill nanosim'
        rsync -are ssh --delete --progress --verbose ./ ${sun_server}:~/fleet/
-       ssh -Y ${sun_server} 'export PATH=/proj/async/cad/linux/bin/:$$PATH; cd ~/fleet/suncvs/marina/testCode; /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java -cp $$HOME/fleet/lib/suncvs.jar com.sun.vlsi.chips.marina.test.MarinaTest -testNum 1006'
+       ssh -Y ${sun_server} 'export PATH=/proj/async/cad/linux/bin/:$$PATH; cd ~/fleet/suncvs/marina/testCode; /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java -cp $$HOME/fleet/lib/suncvs.jar com.sun.vlsi.chips.marina.test.MarinaTest -testNum 3'
 
 electric:
        rsync -are ssh --progress --verbose ${sun_server}:fleet/suncvs/marina/testSims/marina.spi.out ~/marina.spi.out

diff --git a/ships/Dvi.ship b/ships/Dvi.ship
index 669e8d3..6d74b53 100644 (file)
--- a/ships/Dvi.ship
+++ b/ships/Dvi.ship
@@ -33,10 +33,6 @@ percolate up:    gpio_led_n   1
 percolate up:    gpio_led_s   1
 percolate up:    gpio_led_w   1
 
-percolate up:    gpio_led_0   1
-percolate up:    gpio_led_1   1
-percolate up:    gpio_led_2   1
-percolate up:    gpio_led_3   1
 percolate up:    gpio_led_4   1
 percolate up:    gpio_led_5   1
 percolate up:    gpio_led_6   1

diff --git a/ships/ZBT.ship b/ships/ZBT.ship
index 5492613..8bdc540 100644 (file)
--- a/ships/ZBT.ship
+++ b/ships/ZBT.ship
@@ -7,6 +7,11 @@ data  in:    inDataWrite
 
 data  out:   out
 
+percolate up:    gpio_led_0   1
+percolate up:    gpio_led_1   1
+percolate up:    gpio_led_2   1
+percolate up:    gpio_led_3   1
+
 percolate up:      sram_adv_ld_b 1
 percolate up:      sram_bw0 1
 percolate up:      sram_bw1 1
@@ -87,6 +92,23 @@ percolate inout:    sram_flash_d15 1
 
 == FPGA ==============================================================
 
+wire [17:0] wb_adr_i;  // : in std_logic_vector(17 downto 0);
+wire        wb_we_i;   // : in std_logic;
+wire [35:0] wb_dat_i;  // : in std_logic_vector(35 downto 0);
+wire [3:0]  wb_sel_i;  // : in std_logic_vector(3 downto 0);
+wire [35:0] wb_dat_o;  // : out std_logic_vector(35 downto 0);
+
+wire        wb_err_o;  // : out std_logic;
+
+wire        wb_cyc_i;  // : in std_logic;
+wire        wb_stb_i;  // : in std_logic;
+wire [2:0]  wb_cti_i;  // : in std_logic_vector(2 downto 0);
+wire [1:0]  wb_bte_i;  // : in std_logic_vector(1 downto 0);
+
+wire        wb_ack_o;  // : out std_logic;
+
+wire        wb_tga_i;  // : in std_logic := '0' --'0' to mean last (or single) 4 words burst
+
 zbt_top my_zbt_top(
   .clk(clk),
   .reset(rst),
@@ -159,20 +181,31 @@ zbt_top my_zbt_top(
   .SRAM_DQP2(sram_dqp2),
   .SRAM_DQP3(sram_dqp3),
 
-  .wb_adr_i(), // : in std_logic_vector(17 downto 0);
-  .wb_we_i(), // : in std_logic;
-  .wb_dat_i(), // : in std_logic_vector(35 downto 0);
-  .wb_sel_i(), // : in std_logic_vector(3 downto 0);
-  .wb_dat_o(), // : out std_logic_vector(35 downto 0);
-  .wb_cyc_i(), // : in std_logic;
-  .wb_stb_i(), // : in std_logic;
-  .wb_cti_i(), // : in std_logic_vector(2 downto 0);
-  .wb_bte_i(), // : in std_logic_vector(1 downto 0);
-  .wb_ack_o(), // : out std_logic;
-  .wb_err_o(), // : out std_logic;
-  .wb_tga_i() // in std_logic := '0' --'0' to mean last (or single) 4 words burst
+  .wb_adr_i(wb_adr_i),
+  .wb_we_i(wb_we_i),
+  .wb_dat_i(wb_dat_i),
+  .wb_sel_i(wb_sel_i),
+  .wb_dat_o(wb_dat_o),
+  .wb_cyc_i(wb_cyc_i),
+  .wb_stb_i(wb_stb_i),
+  .wb_cti_i(wb_cti_i),
+  .wb_bte_i(wb_bte_i),
+  .wb_ack_o(wb_ack_o),
+  .wb_err_o(wb_err_o),
+  .wb_tga_i(wb_tga_i)
  );
-/*
+
+assign wb_sel_i = 4'b0000;
+
+assign gpio_led_0 = wb_err_o_r;
+always @(posedge clk) begin
+  if (rst) begin
+    wb_err_o_r <= 0;
+  end else begin
+    wb_err_o_r <= wb_err_o_r | wb_err_o;
+  end
+end
+
 // custom code //////////////////////////////////////////////////////////////////////////////
 
 reg  [37:0] out_d;
@@ -182,10 +215,6 @@ assign out_d_ = out_d;
 always @(posedge clk) begin
   if (rst) begin
     `reset
-    app_wdf_wren <= 0;
-    app_af_wren  <= 0;
-    read_waiting <= 0;
-    burst_count  <= 0;
 
   end else begin
     `cleanup