-ship: Video
+ship: Dvi
== Ports ===========================================================
data in: inX
data in: inY
data in: inData
+data in: inAddrRead
+data in: inAddrWrite
+data in: inDataWrite
+
+data out: out
+
percolate up: dvi_d0 1
percolate up: dvi_d1 1
percolate up: dvi_d2 1
percolate up: dvi_iic_scl 1
percolate inout: dvi_iic_sda 1
+percolate up: gpio_led_0 1
+percolate up: gpio_led_1 1
+percolate up: gpio_led_2 1
+percolate up: gpio_led_3 1
+
+percolate up: sram_adv_ld_b 1
+percolate up: sram_bw0 1
+percolate up: sram_bw1 1
+percolate up: sram_bw2 1
+percolate up: sram_bw3 1
+percolate up: sram_clk 1
+percolate up: sram_cs_b 1
+percolate up: sram_flash_a0 1
+percolate up: sram_flash_a1 1
+percolate up: sram_flash_a2 1
+percolate up: sram_flash_a3 1
+percolate up: sram_flash_a4 1
+percolate up: sram_flash_a5 1
+percolate up: sram_flash_a6 1
+percolate up: sram_flash_a7 1
+percolate up: sram_flash_a8 1
+percolate up: sram_flash_a9 1
+percolate up: sram_flash_a10 1
+percolate up: sram_flash_a11 1
+percolate up: sram_flash_a12 1
+percolate up: sram_flash_a13 1
+percolate up: sram_flash_a14 1
+percolate up: sram_flash_a15 1
+percolate up: sram_flash_a16 1
+percolate up: sram_flash_a17 1
+percolate up: sram_flash_a18 1
+percolate up: sram_flash_a19 1
+percolate up: sram_flash_a20 1
+percolate up: sram_flash_a21 1
+percolate up: sram_flash_we_b 1
+percolate up: sram_mode 1
+percolate up: sram_oe_b 1
+
+percolate inout: sram_dqp0 1
+percolate inout: sram_dqp1 1
+percolate inout: sram_dqp2 1
+percolate inout: sram_dqp3 1
+
+percolate inout: sram_flash_d0 1
+percolate inout: sram_flash_d1 1
+percolate inout: sram_flash_d2 1
+percolate inout: sram_flash_d3 1
+percolate inout: sram_flash_d4 1
+percolate inout: sram_flash_d5 1
+percolate inout: sram_flash_d6 1
+percolate inout: sram_flash_d7 1
+percolate inout: sram_flash_d8 1
+percolate inout: sram_flash_d9 1
+percolate inout: sram_flash_d10 1
+percolate inout: sram_flash_d11 1
+percolate inout: sram_flash_d12 1
+percolate inout: sram_flash_d13 1
+percolate inout: sram_flash_d14 1
+percolate inout: sram_flash_d15 1
+percolate inout: sram_d16 1
+percolate inout: sram_d17 1
+percolate inout: sram_d18 1
+percolate inout: sram_d19 1
+percolate inout: sram_d20 1
+percolate inout: sram_d21 1
+percolate inout: sram_d22 1
+percolate inout: sram_d23 1
+percolate inout: sram_d24 1
+percolate inout: sram_d25 1
+percolate inout: sram_d26 1
+percolate inout: sram_d27 1
+percolate inout: sram_d28 1
+percolate inout: sram_d29 1
+percolate inout: sram_d30 1
+percolate inout: sram_d31 1
+
== FPGA ==============================================================
wire [9:0] x_coord;
reg we;
- wire [2:0] mem_out;
+ reg [31:0] mem_out;
wire [18:0] inAddr;
wire [18:0] vga_pixel_addr_;
reg [18:0] vga_pixel_addr;
+ reg [18:0] last_vga_pixel_addr;
+
+reg write_enable;
+reg oe;
+reg [2:0] wait_cycles;
+reg was_write;
+reg was_video;
+reg [37:0] addr;
+wire [31:0] data_out;
+reg [37:0] out_d;
+
+assign out_d_ = out_d;
+
+assign sram_flash_a0 = addr[0];
+assign sram_flash_a1 = addr[1];
+assign sram_flash_a2 = addr[2];
+assign sram_flash_a3 = addr[3];
+assign sram_flash_a4 = addr[4];
+assign sram_flash_a5 = addr[5];
+assign sram_flash_a6 = addr[6];
+assign sram_flash_a7 = addr[7];
+assign sram_flash_a8 = addr[8];
+assign sram_flash_a9 = addr[9];
+assign sram_flash_a10 = addr[10];
+assign sram_flash_a11 = addr[11];
+assign sram_flash_a12 = addr[12];
+assign sram_flash_a13 = addr[13];
+assign sram_flash_a14 = addr[14];
+assign sram_flash_a15 = addr[15];
+assign sram_flash_a16 = addr[16];
+assign sram_flash_a17 = addr[17];
+assign sram_flash_a18 = addr[18];
+assign sram_flash_a19 = addr[19];
+assign sram_flash_a20 = addr[20];
+assign sram_flash_a21 = addr[21];
+
+assign data_out[0] = sram_flash_d0; assign sram_flash_d0 = oe ? 1'bz : inDataWrite_d[0];
+assign data_out[1] = sram_flash_d1; assign sram_flash_d1 = oe ? 1'bz : inDataWrite_d[1];
+assign data_out[2] = sram_flash_d2; assign sram_flash_d2 = oe ? 1'bz : inDataWrite_d[2];
+assign data_out[3] = sram_flash_d3; assign sram_flash_d3 = oe ? 1'bz : inDataWrite_d[3];
+assign data_out[4] = sram_flash_d4; assign sram_flash_d4 = oe ? 1'bz : inDataWrite_d[4];
+assign data_out[5] = sram_flash_d5; assign sram_flash_d5 = oe ? 1'bz : inDataWrite_d[5];
+assign data_out[6] = sram_flash_d6; assign sram_flash_d6 = oe ? 1'bz : inDataWrite_d[6];
+assign data_out[7] = sram_flash_d7; assign sram_flash_d7 = oe ? 1'bz : inDataWrite_d[7];
+assign data_out[8] = sram_flash_d8; assign sram_flash_d8 = oe ? 1'bz : inDataWrite_d[8];
+assign data_out[9] = sram_flash_d9; assign sram_flash_d9 = oe ? 1'bz : inDataWrite_d[9];
+assign data_out[10] = sram_flash_d10; assign sram_flash_d10 = oe ? 1'bz : inDataWrite_d[10];
+assign data_out[11] = sram_flash_d11; assign sram_flash_d11 = oe ? 1'bz : inDataWrite_d[11];
+assign data_out[12] = sram_flash_d12; assign sram_flash_d12 = oe ? 1'bz : inDataWrite_d[12];
+assign data_out[13] = sram_flash_d13; assign sram_flash_d13 = oe ? 1'bz : inDataWrite_d[13];
+assign data_out[14] = sram_flash_d14; assign sram_flash_d14 = oe ? 1'bz : inDataWrite_d[14];
+assign data_out[15] = sram_flash_d15; assign sram_flash_d15 = oe ? 1'bz : inDataWrite_d[15];
+assign data_out[16] = sram_d16; assign sram_d16 = oe ? 1'bz : inDataWrite_d[16];
+assign data_out[17] = sram_d17; assign sram_d17 = oe ? 1'bz : inDataWrite_d[17];
+assign data_out[18] = sram_d18; assign sram_d18 = oe ? 1'bz : inDataWrite_d[18];
+assign data_out[19] = sram_d19; assign sram_d19 = oe ? 1'bz : inDataWrite_d[19];
+assign data_out[20] = sram_d20; assign sram_d20 = oe ? 1'bz : inDataWrite_d[20];
+assign data_out[21] = sram_d21; assign sram_d21 = oe ? 1'bz : inDataWrite_d[21];
+assign data_out[22] = sram_d22; assign sram_d22 = oe ? 1'bz : inDataWrite_d[22];
+assign data_out[23] = sram_d23; assign sram_d23 = oe ? 1'bz : inDataWrite_d[23];
+assign data_out[24] = sram_d24; assign sram_d24 = oe ? 1'bz : inDataWrite_d[24];
+assign data_out[25] = sram_d25; assign sram_d25 = oe ? 1'bz : inDataWrite_d[25];
+assign data_out[26] = sram_d26; assign sram_d26 = oe ? 1'bz : inDataWrite_d[26];
+assign data_out[27] = sram_d27; assign sram_d27 = oe ? 1'bz : inDataWrite_d[27];
+assign data_out[28] = sram_d28; assign sram_d28 = oe ? 1'bz : inDataWrite_d[28];
+assign data_out[29] = sram_d29; assign sram_d29 = oe ? 1'bz : inDataWrite_d[29];
+assign data_out[30] = sram_d30; assign sram_d30 = oe ? 1'bz : inDataWrite_d[30];
+assign data_out[31] = sram_d31; assign sram_d31 = oe ? 1'bz : inDataWrite_d[31];
+
+assign sram_mode = 0;
+assign sram_clk = clk;
+assign sram_bw0 = ~write_enable;
+assign sram_bw1 = ~write_enable;
+assign sram_bw2 = ~write_enable;
+assign sram_bw3 = ~write_enable;
+assign sram_flash_we_b = ~write_enable;
+assign sram_adv_ld_b = 0;
+assign sram_cs_b = 0;
+assign sram_oe_b = ~oe;
assign inAddr = inX_d + { inY_d[8:0], 7'b0000000 } + { inY_d[8:0], 10'b0000000000 };
assign vga_pixel_addr_ = x_coord + { y_coord[8:0], 7'b0000000 } + { y_coord[8:0], 10'b0000000000 };
- assign dvi_red = { mem_out[2], 7'b0 };
- assign dvi_green = { mem_out[1], 7'b0 };
- assign dvi_blue = { mem_out[0], 7'b0 };
+ assign dvi_red = mem_out[23:16];
+ assign dvi_green = mem_out[15:8];
+ assign dvi_blue = mem_out[7:0];
+ wire [2:0] mem_out_old;
vram vram(clk, ~rst, we,
inAddr[18:0],
vga_pixel_addr,
inData_d, ,
- mem_out);
+ mem_out_old);
always @(posedge pix_clk) begin
vga_pixel_addr <= vga_pixel_addr_;
end
- always @(posedge clk) begin
-
- if (rst) begin
- `reset
- end else begin
- `cleanup
-
- if (`inX_full && `inY_full && `inData_full) begin
- we <= 1;
- `drain_inX
- `drain_inY
- `drain_inData
+always @(posedge clk) begin
+ if (rst) begin
+ `reset
+ wait_cycles <= 0;
+
+ end else begin
+ `cleanup
+
+ write_enable <= 0;
+ oe <= 1;
+ if (wait_cycles == 1) begin
+ if (was_video) begin
+ mem_out <= data_out;
+ end else if (was_write) begin
+ out_d <= { 1'b1, 37'b0 };
+ `fill_out
+ `drain_inDataWrite
+ `drain_inAddrWrite
+ oe <= 0;
end else begin
- we <= 0;
+ out_d <= { 1'b0, data_out };
+ `fill_out
+ `drain_inAddrRead
end
+ wait_cycles <= 0;
+
+ end else if (wait_cycles != 0) begin
+ wait_cycles <= wait_cycles-1;
+
+ end else if (`inAddrWrite_full && `inDataWrite_full) begin
+ write_enable <= 1;
+ was_write <= 1;
+ was_video <= 0;
+ wait_cycles <= 1;
+ addr <= { inAddrWrite_d, 1'b0 };
+
+ end else if (`inAddrRead_full) begin
+ write_enable <= 0;
+ was_write <= 0;
+ was_video <= 0;
+ wait_cycles <= 3;
+ addr <= { inAddrRead_d, 1'b0 };
+
+ end else if (last_vga_pixel_addr != vga_pixel_addr) begin
+ write_enable <= 0;
+ was_write <= 0;
+ was_video <= 1;
+ wait_cycles <= 3;
+ addr <= { vga_pixel_addr, 1'b0 };
+ last_vga_pixel_addr <= vga_pixel_addr;
+ end
+ if (`inX_full && `inY_full && `inData_full) begin
+ we <= 1;
+ `drain_inX
+ `drain_inY
+ `drain_inData
+ end else begin
+ we <= 0;
end
- end
+ end
+end
== UCF ===============================================================
NET gpio_led_6 LOC="AD24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET gpio_led_7 LOC="AE24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+######
+
+NET sram_adv_ld_b LOC="H8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_bw0 LOC="D10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_bw1 LOC="D11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_bw2 LOC="J11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_bw3 LOC="K11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_clk LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_clk LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_cs_b LOC="J10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d16 LOC="N10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d17 LOC="E13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d18 LOC="E12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d19 LOC="L9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d20 LOC="M10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d21 LOC="E11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d22 LOC="F11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d23 LOC="L8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d24 LOC="M8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d25 LOC="G12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d26 LOC="G11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d27 LOC="C13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d28 LOC="B13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d29 LOC="K9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d30 LOC="K8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d31 LOC="J9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_dqp0 LOC="D12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_dqp1 LOC="C12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_dqp2 LOC="H10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_dqp3 LOC="H9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_flash_a0 LOC="K12"; # Bank 1, Vcco=3.3V
+NET sram_flash_a1 LOC="K13"; # Bank 1, Vcco=3.3V
+NET sram_flash_a2 LOC="H23"; # Bank 1, Vcco=3.3V
+NET sram_flash_a3 LOC="G23"; # Bank 1, Vcco=3.3V
+NET sram_flash_a4 LOC="H12"; # Bank 1, Vcco=3.3V
+NET sram_flash_a5 LOC="J12"; # Bank 1, Vcco=3.3V
+NET sram_flash_a6 LOC="K22"; # Bank 1, Vcco=3.3V
+NET sram_flash_a7 LOC="K23"; # Bank 1, Vcco=3.3V
+NET sram_flash_a8 LOC="K14"; # Bank 1, Vcco=3.3V
+NET sram_flash_a9 LOC="L14"; # Bank 1, Vcco=3.3V
+NET sram_flash_a10 LOC="H22"; # Bank 1, Vcco=3.3V
+NET sram_flash_a11 LOC="G22"; # Bank 1, Vcco=3.3V
+NET sram_flash_a12 LOC="J15"; # Bank 1, Vcco=3.3V
+NET sram_flash_a13 LOC="K16"; # Bank 1, Vcco=3.3V
+NET sram_flash_a14 LOC="K21"; # Bank 1, Vcco=3.3V
+NET sram_flash_a15 LOC="J22"; # Bank 1, Vcco=3.3V
+NET sram_flash_a16 LOC="L16"; # Bank 1, Vcco=3.3V
+NET sram_flash_a17 LOC="L15"; # Bank 1, Vcco=3.3V
+NET sram_flash_a18 LOC="L20"; # Bank 1, Vcco=3.3V
+NET sram_flash_a19 LOC="L21"; # Bank 1, Vcco=3.3V
+NET sram_flash_a20 LOC="AE23"; # Bank 2, Vcco=3.3V
+NET sram_flash_a21 LOC="AE22"; # Bank 2, Vcco=3.3V
+NET sram_flash_d0 LOC="AD19"; # Bank 2, Vcco=3.3V
+NET sram_flash_d1 LOC="AE19"; # Bank 2, Vcco=3.3V
+NET sram_flash_d2 LOC="AE17"; # Bank 2, Vcco=3.3V
+NET sram_flash_d3 LOC="AF16"; # Bank 2, Vcco=3.3V
+NET sram_flash_d4 LOC="AD20"; # Bank 2, Vcco=3.3V
+NET sram_flash_d5 LOC="AE21"; # Bank 2, Vcco=3.3V
+NET sram_flash_d6 LOC="AE16"; # Bank 2, Vcco=3.3V
+NET sram_flash_d7 LOC="AF15"; # Bank 2, Vcco=3.3V
+NET sram_flash_d8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_we_b LOC="AF20"; # Bank 2, Vcco=3.3V
+NET sram_mode LOC="A13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_oe_b LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+
+
+
== TeX ==============================================================
== Fleeterpreter ====================================================
projects / fleet.git / commitdiff