reg [(`DATAWIDTH-1):0] mem [4:0];
reg [5:0] depth;
+ reg skip;
+ initial depth = 0;
always @(posedge clk) begin
- if (depth < 32) begin
- `onread(push_r, push_a)
- pop_d = push_d;
- mem[depth] <= push_d;
- depth = depth + 1;
- end
- end
+ skip = 0;
if (depth > 0) begin
- `onwrite(pop_r, pop_d)
- depth = depth - 1;
- if (depth > 0) begin
- pop_d = mem[depth];
+ `onwrite(pop_r, pop_a)
+ if (depth > 1) begin
+ pop_d <= mem[depth-2];
end
+ depth <= depth - 1;
+ skip = 1;
+ end
+ end
+ if (!skip && depth < 32) begin
+ `onread(push_r, push_a)
+ pop_d <= push_d;
+ mem[depth] <= push_d;
+ depth <= depth + 1;
end
end
end
#expect 1
#expect 0
+debug.in: [*] take, deliver;
stack.push: [5] take, deliver; notify stack.pop;
+stack.pop: wait; [*] take, sendto debug.in;
+
0: sendto stack.push;
1: sendto stack.push;
2: sendto stack.push;
3: sendto stack.push;
4: sendto stack.push;
-stack.pop: wait; [*] take, sendto debug.in;
-debug.in: [*] take, deliver;
+
+