change rst to high-active

diff --git a/ships/Alu.ship b/ships/Alu.ship
index 177592b..2588447 100644 (file)
--- a/ships/Alu.ship
+++ b/ships/Alu.ship
@@ -180,7 +180,7 @@ public void service() {
           0;
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
       out_draining <= 0;
     end else begin

diff --git a/ships/CarrySaveAdder.ship b/ships/CarrySaveAdder.ship
index db0312d..03722c6 100644 (file)
--- a/ships/CarrySaveAdder.ship
+++ b/ships/CarrySaveAdder.ship
@@ -71,7 +71,7 @@ public void service() {
   endgenerate
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
       state <= 0;
     end else begin

diff --git a/ships/Counter.ship b/ships/Counter.ship
index b8155f5..06a87ce 100644 (file)
--- a/ships/Counter.ship
+++ b/ships/Counter.ship
@@ -110,7 +110,7 @@ public void service() {
   // FIXME: REPEAT with a count of zero will not work properly
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
       full <= 0;
       out_draining <= 0;

diff --git a/ships/DDR2.ship b/ships/DDR2.ship
index 25b81b1..1092f73 100644 (file)
--- a/ships/DDR2.ship
+++ b/ships/DDR2.ship
@@ -225,7 +225,7 @@ DDR2SDRAM DDR2SDRAM(
 
   always @(posedge clk) begin
 
-    if (!rst) begin
+    if (rst) begin
       `reset
       CommandValid <= 0;
       DataOutReady <= 0;

diff --git a/ships/DRAM.ship b/ships/DRAM.ship
index cc665fc..161928e 100644 (file)
--- a/ships/DRAM.ship
+++ b/ships/DRAM.ship
@@ -66,7 +66,7 @@ percolate inout:         ddr1_DQ            32
           .ddr_cke( ddr1_CE_pin ),
    
           .clk(clk),
-          .reset(!rst),
+          .reset(rst),
           .rot(3'b100),
    
           .fml_wr(!dram_isread && dram_addr_r),
@@ -80,7 +80,7 @@ percolate inout:         ddr1_DQ            32
 
   always @(posedge clk) begin
 
-    if (!rst) begin
+    if (rst) begin
       `reset
       dram_isread <= 0;
       dram_addr_r <= 0;

diff --git a/ships/Debug.ship b/ships/Debug.ship
index aa17399..4ce4f09 100644 (file)
--- a/ships/Debug.ship
+++ b/ships/Debug.ship
@@ -63,13 +63,13 @@ public void service() {
   wire break;
   wire uart_cts;
   assign uart_cts = 0;
-  assign rst_out = rst_in && !break;
+  assign rst_out = rst_in || break;
 
   // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
   // using a 33Mhz clock,
   //   33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1
-  sasc_brg sasc_brg(clk, rst_in, 215, 1, sio_ce, sio_ce_x4);
-  sasc_top sasc_top(clk, rst_in,
+  sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
+  sasc_top sasc_top(clk, !rst_in,
                     uart_in,
                     uart_out,
                     uart_cts,
@@ -92,7 +92,7 @@ public void service() {
 
    // fpga -> host
    always @(posedge clk) begin
-     if (!rst) begin
+     if (rst) begin
        count_in  <= 0;
        count_out <= 0;
        `reset

diff --git a/ships/Lut3.ship b/ships/Lut3.ship
index 17063d8..dc56e2b 100644 (file)
--- a/ships/Lut3.ship
+++ b/ships/Lut3.ship
@@ -75,7 +75,7 @@ is considered ``bit zero'').
   assign lut = inLut_d[7:0];
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
       out_draining <= 0;
     end else begin

diff --git a/ships/Memory.ship b/ships/Memory.ship
index f9e5269..41e728c 100644 (file)
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -154,7 +154,7 @@ sequence guarantee problem mentioned in the previous paragraph.
   always @(posedge clk) begin
     write_flag = 0;
 
-    if (!rst) begin
+    if (rst) begin
       `reset
       cursor      = 0;
       counter     = 0;

diff --git a/ships/Rotator.ship b/ships/Rotator.ship
index 8291e6a..810948b 100644 (file)
--- a/ships/Rotator.ship
+++ b/ships/Rotator.ship
@@ -47,7 +47,7 @@ public void service() {
   assign shamt_eq = (shamt[5:0] == (inAmount_d[5:0]));
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
       full <= 0;
     end else begin

diff --git a/ships/Video.ship b/ships/Video.ship
index f9777fb..b8ee01b 100644 (file)
--- a/ships/Video.ship
+++ b/ships/Video.ship
@@ -91,11 +91,11 @@ percolate up:         vga_clkout  1
 
   assign inAddr = inX_d + (inY_d * 640);
 
-  vram vram(clk, rst, we, inAddr[18:0], vga_pixel_addr_[20:2], inData_d, , mem_out);
+  vram vram(clk, !rst, we, inAddr[18:0], vga_pixel_addr_[20:2], inData_d, , mem_out);
 
   wb_vga wb_vga(
        .wb_clk_i(clk),
-       .wb_rst_i(!rst),
+       .wb_rst_i(rst),
        
        .fbwb_adr_o(vga_pixel_addr_),
        .fbwb_stb_o(vga_pixel_r),
@@ -117,7 +117,7 @@ percolate up:         vga_clkout  1
 
   always @(posedge clk) begin
 
-    if (!rst) begin
+    if (rst) begin
       `reset
     end else begin
       `cleanup

diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java
index 13d9e6a..70f83fe 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Fpga.java
+++ b/src/edu/berkeley/fleet/fpga/Fpga.java
@@ -309,7 +309,7 @@ public class Fpga extends FleetTwoFleet {
                 pw.println("                    in_r,    in_a__, in_d,");
                 pw.println("                    out_r__, out_a,  out_d_);");
                 pw.println("  always @(posedge clk) begin");
-                pw.println("    if (!rst) begin");
+                pw.println("    if (rst) begin");
                 pw.println("      `reset");
                 pw.println("    end else begin");
                 pw.println("      `cleanup");

diff --git a/src/edu/berkeley/fleet/fpga/ramfifo.inc b/src/edu/berkeley/fleet/fpga/ramfifo.inc
index f8977f5..6e6e6af 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ramfifo.inc
+++ b/src/edu/berkeley/fleet/fpga/ramfifo.inc
@@ -56,7 +56,7 @@ module `MODULE_NAME(clk, rst,
     reg inctail;
 
     always @(posedge clk) begin 
-        if (!rst) begin
+        if (rst) begin
           out_r <= 0;
           in_a <= 0;
           control <= 0;

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index cb1e8bd..cd0deea 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -689,7 +689,7 @@ public class Verilog {
 
             if (isRoot) {
                 pw.println("  assign rst    = rst_out;");
-                pw.println("  assign rst_in = rst_pin;");
+                pw.println("  assign rst_in = !rst_pin;");
             }
 
             for(String name : ports.keySet()) pw.println("    " + ports.get(name).getDeclaration());
@@ -700,7 +700,7 @@ public class Verilog {
             for(WireValue wv : wires.values()) pw.println("    " + wv.getAssignments());
             for(InstantiatedModule m : instantiatedModules) m.dump(pw);
             pw.println("always @(posedge clk) begin");
-            pw.println("  if (!rst) begin");
+            pw.println("  if (rst) begin");
             for(Latch l : latches.values()) pw.println(l.getResetCode());
             for(StateWire sw : statewires.values()) pw.println(sw.getResetCode());
             for(Port p : ports.values()) pw.println(p.getResetCode());