updated demo code

diff --git a/contrib/dcache-demo.fleet b/contrib/dcache-demo.fleet
new file mode 100644 (file)
index 0000000..8fee352
--- /dev/null
+++ b/contrib/dcache-demo.fleet
@@ -0,0 +1,42 @@
+
+// ships required in order to run this code
+#ship debug        : Debug
+#ship dcache       : Dcache
+#ship fifo         : Fifo
+
+// dumb configurations
+debug.data:        [*] take, deliver;
+dcache.write_addr: [*] take, deliver;
+dcache.write_data: [*] take, deliver;
+dcache.read_addr:  [*] take, deliver;
+fifo.in:           [*] take, deliver;
+
+// addresses and values to initialize the dcache with
+1:  sendto dcache.write_addr;
+2:  sendto dcache.write_addr;
+3:  sendto dcache.write_addr;
+4:  sendto dcache.write_addr;
+11: sendto dcache.write_data;
+12: sendto dcache.write_data;
+13: sendto dcache.write_data;
+14: sendto dcache.write_data;
+
+// send write-completion tokens to the fifo output
+dcache.write_done:
+  [*] take, sendto fifo.out;
+
+// when the write-completion tokens accumulate, unleash
+// the read addresses
+fifo.out:
+  [4] wait;
+  [4] take, sendto dcache.read_addr;
+
+// read addresses
+4:  sendto fifo.in;
+3:  sendto fifo.in;
+2:  sendto fifo.in;
+1:  sendto fifo.in;
+
+// data read from dcache goes to the debug ship
+dcache.read_data:
+  [*] take, sendto debug.data;

diff --git a/contrib/demo.fleet b/contrib/demo.fleet
index bead521..bd4377e 100644 (file)
--- a/contrib/demo.fleet
+++ b/contrib/demo.fleet
@@ -1,38 +1,13 @@
 #include "contrib/demo.ships"
 
-// values and addresses to write
-1: sendto mem.write_addr;
-2: sendto mem.write_addr;
-3: sendto mem.write_addr;
-9: sendto mem.write_data;
-8: sendto mem.write_data;
-7: sendto mem.write_data;
-
-// memory write ports accept the values
-mem.write_addr:  [*] take, deliver;
-mem.write_data:  [*] take, deliver;
-
-// once all three are written, cue the fifo
-mem.write_done:
-  [3] take;
-  ack fifo.out;
-
-// meanwhile, the fifo is sitting on a set of read addresses
-fifo.in: [*] take, deliver;
-1: sendto fifo.in;
-2: sendto fifo.in;
-3: sendto fifo.in;
-1: sendto fifo.in;
-1: sendto fifo.in;
-1: sendto fifo.in;
-
-// when it gets the ack, it issues them all to the memory read unit
-fifo.out:
-  wait;
-  [*] take, sendto mem.read_addr;
-
-// values read from memory go to debug (which accepts them)
-mem.read_addr:   [*] take, deliver;
-mem.read_data:   [*] take, sendto debug.data;
-debug.data:      [*] take, deliver;
+BOB:          sendto icache.cbd;
+icache.cbd:   [*] take, deliver;
+debug.data:   [*] take, deliver;
+
+BOB: {
+  12:           sendto debug.data;
+  13:           sendto debug.data;
+  14:           sendto debug.data;
+  BOB:          sendto icache.cbd;
+}
 

diff --git a/contrib/demo.ships b/contrib/demo.ships
index 4fdef28..dbb3a83 100644 (file)
--- a/contrib/demo.ships
+++ b/contrib/demo.ships
@@ -1,10 +1,9 @@
-#import edu.berkeley.fleet.ships
-
 #ship alu2         : Alu2
 #ship debug        : Debug
 #ship execute      : Execute
 #ship fifo         : Fifo
-#ship mem          : Mem
+//#ship mem          : Mem
+#ship icache         : Icache
 
 
 // alu1

diff --git a/contrib/icache-demo.fleet b/contrib/icache-demo.fleet
new file mode 100644 (file)
index 0000000..c0ebc46
--- /dev/null
+++ b/contrib/icache-demo.fleet
@@ -0,0 +1,25 @@
+
+// ships required in order to run this code
+#ship debug        : Debug
+#ship icache       : Icache
+
+// instructions not in any codebag are part of the "root codebag"
+// which is dispatched when the code is loaded
+
+debug.data:   deliver;
+BOB:          sendto icache.cbd;
+icache.cbd:   [*] take, deliver;
+debug.data:   [*] take, deliver;
+
+
+// This codebag illustrates how to do a loop.  Notice that this
+// is actually an uncontrolled data emitter -- it could clog the
+//  switch fabric!
+
+BOB: {
+  12:           sendto debug.data;
+  13:           sendto debug.data;
+  14:           sendto debug.data;
+  BOB:          sendto icache.cbd;
+}
+