master clear works (at least for memory ship)

diff --git a/ships/Memory.ship b/ships/Memory.ship
index e9f1e51..cb08c22 100644 (file)
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -265,8 +265,14 @@ module memory (clk, rst,
       dhorn_full <= 0;
       command_valid <= 0;
 /*
-      preload_size <= 0;
+      // uncommenting either of these causes headaches
 */
+      preload_size <= 0;
+      preload_pos <= 0;
+      temp_base = 0;
+      temp_size = 0;
+
+
       launched <= 0;
       command_valid_read <= 0;
       write_flag <= 0;
@@ -342,6 +348,7 @@ module memory (clk, rst,
         `onread(preload_r, preload_a)
           if (preload_size == 0) begin
             preload_size     <= preload_d;
+            preload_pos      <= 0;
           end else if (!launched) begin
             write_flag <= 1;
             write_data <= preload_d;

diff --git a/src/edu/berkeley/fleet/fpga/Server.java b/src/edu/berkeley/fleet/fpga/Server.java
index 7f1fbfd..a3a4099 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Server.java
+++ b/src/edu/berkeley/fleet/fpga/Server.java
@@ -47,7 +47,7 @@ public class Server {
             synchronized(Server.class) {
                 try {
                     this.sp = new RXTXPort("/dev/ttyS0");
-                    //sp.sendBreak(500);
+                    sp.sendBreak(500);
                     try {
                         _run();
                     } finally {
@@ -75,6 +75,7 @@ public class Server {
                 System.err.println("sending instructions...");
 
                 sp.setSerialPortParams(9600, SerialPort.DATABITS_8, SerialPort.STOPBITS_1, SerialPort.PARITY_NONE);
+                sp.setFlowControlMode(sp.FLOWCONTROL_RTSCTS_IN | sp.FLOWCONTROL_RTSCTS_OUT);
                 final OutputStream fos = sp.getOutputStream();
                 final InputStream fis = sp.getInputStream();
 
@@ -115,6 +116,7 @@ public class Server {
                         if (closed) return;
                         val = fis.read();
                         if (val==-1) break;
+                        System.err.println("byte: 0x"+Integer.toString(val & 0xff, 16));
                         os.write((byte)val);
                         os.flush();
                         result |= ((long)val) << (i * 8);

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index 9c6fcb8..b84287f 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -17,7 +17,8 @@ module main
 
   wire clk;
   assign clk = sys_clk_pin;
-  wire break;
+  wire break_o;
+  reg break_last;
   wire rst;
   assign rst = sys_rst_pin;
 
@@ -32,6 +33,7 @@ module main
   reg we;
   reg re;
   reg [7:0] data_to_host_r;
+  assign data_to_host = data_to_host_r;
 
   wire ser_rst;
   reg ser_rst_r;
@@ -54,7 +56,10 @@ module main
                     data_to_host_write_enable,
                     data_to_host_full,
                     data_to_fleet_empty,
-                    break);
+                    break_o);
+
+   always @(posedge clk) break_last <= break_o;
+   assign break = break_o && !break_last;
 
    reg data_to_host_write_enable_reg;
    reg data_to_fleet_read_enable_reg;
@@ -67,11 +72,12 @@ module main
    wire root_out_a;
    wire root_out_r;
    wire [7:0] root_in_d;
+   wire [7:0] root_out_d;
 
 
    root my_root(clk, rst && !break, 
                 root_in_r,  root_in_a,  root_in_d,
-                root_out_r, root_out_a, data_to_host);
+                root_out_r, root_out_a, root_out_d);
 /*
    fifo4 my_root(clk, rst,
                 root_in_r,  root_in_a,  root_in_d,
@@ -87,8 +93,15 @@ module main
    always @(posedge clk)
    begin
      data_to_host_write_enable_reg = 0;
+/*
+     if (break) begin
+       data_to_host_write_enable_reg = 1;
+       data_to_host_r <= 98;
+     end else
+*/
      if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
        data_to_host_write_enable_reg = 1;
+       data_to_host_r <= root_out_d;
        root_out_a_reg = 1;
      end else if (root_out_a_reg && !root_out_r) begin
        root_out_a_reg = 0;

diff --git a/src/edu/berkeley/fleet/fpga/sasc_top.v b/src/edu/berkeley/fleet/fpga/sasc_top.v
index 1ebb15a..257597b 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/sasc_top.v
+++ b/src/edu/berkeley/fleet/fpga/sasc_top.v
@@ -244,7 +244,7 @@ assign break_o = break_r;
 always @(posedge clk)
        rx_valid <= #1 (rx_bit_cnt == 4'h9) && (rxd_s == STOP_BIT);
 always @(posedge clk)
-       break_r  <= #1 (rx_bit_cnt == 4'h9) && (rxr[9:1]==8'b0) && (rxd_s == START_BIT);
+       break_r  <= #1 /*(rx_bit_cnt == 4'h9) &&*/ (rxr[9:0]==10'b0) && (rxd_dly == 5'b0) && (rxd_s == 0) && (rxd_r == 0);
 
 always @(posedge clk)
        rx_valid_r <= #1 rx_valid;