alter Alu1 test to work around fpga anomoly

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index ee942cd..1ac349d 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -92,6 +92,7 @@ The result of this operation is then made available at {\tt out}.
 
 == Test ==============================================================================
 // expected output
+
 #expect 10
 #expect 8
 #expect 9
@@ -105,18 +106,19 @@ debug.in:   [*] take, deliver;
 alu1.in:
   literal 9;
   load repeat counter with 4; deliver;
-  [*] take, deliver;
+  take, deliver;
 
 alu1.out:
   load repeat counter with 4; take, sendto debug.in;
   sendto alu1.in;
-  [*] take, sendto debug.in;
+  take, sendto debug.in;
 
 alu1.inOp:
    literal 1; deliver;
    literal 2; deliver;
    literal 3; deliver;
-   literal 0; load repeat counter with 2; deliver;
+   literal 0; deliver;
+   literal 0; deliver;
 
 
 == Contributors =========================================================