add port percolation, use it for DRAM.ship

diff --git a/ships/DRAM.ship b/ships/DRAM.ship
index 2607b28..e3bdbb6 100644 (file)
--- a/ships/DRAM.ship
+++ b/ships/DRAM.ship
@@ -7,6 +7,18 @@ data  in:    inDataWrite
 
 data  out:   out
 
+percolate up:     dram_addr_                32
+percolate up:     dram_addr_r_              1
+percolate down:   dram_addr_a               1
+percolate up:     dram_isread_              1
+percolate up:     dram_write_data_          64
+percolate up:     dram_write_data_push_     1
+percolate down:   dram_write_data_full      1
+percolate down:   dram_read_data            64
+percolate up:     dram_read_data_pop_       1
+percolate down:   dram_read_data_empty      1
+percolate down:   dram_read_data_latency    2
+
 == TeX ==============================================================
 
 == Fleeterpreter ====================================================

diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java
index 9afdcc6..0f751b2 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Fpga.java
+++ b/src/edu/berkeley/fleet/fpga/Fpga.java
@@ -13,6 +13,7 @@ import java.io.*;
 import edu.berkeley.fleet.two.*;
 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
+import static edu.berkeley.fleet.fpga.verilog.Verilog.PercolatedPort;
 
 
 public class Fpga extends FleetTwoFleet {
@@ -332,18 +333,9 @@ public class Fpga extends FleetTwoFleet {
                 pw.println("    , out_a");
                 pw.println("    , out_d_");
             }
-            if (filename.equals("dram")) {
-                pw.println("    , dram_addr_");
-                pw.println("    , dram_addr_r_");
-                pw.println("    , dram_addr_a");
-                pw.println("    , dram_isread_");
-                pw.println("    , dram_write_data_");
-                pw.println("    , dram_write_data_push_");
-                pw.println("    , dram_write_data_full");
-                pw.println("    , dram_read_data");
-                pw.println("    , dram_read_data_pop_");
-                pw.println("    , dram_read_data_empty");
-                pw.println("    , dram_read_data_latency");
+            for(PercolatedPort pp : sd.percolatedPorts) {
+                pw.print("    , ");
+                pw.println(pp.name);
             }
             if (filename.equals("ddr2")) {
                 pw.println("    , ddr2_addr_");
@@ -374,18 +366,14 @@ public class Fpga extends FleetTwoFleet {
             pw.println();
             pw.println("    input clk;");
             pw.println("    input rst;");
-            if (filename.equals("dram")) {
-                pw.println("output  [31:0] dram_addr_;");
-                pw.println("output         dram_addr_r_;");
-                pw.println("input          dram_addr_a;");
-                pw.println("output         dram_isread_;");
-                pw.println("output  [63:0] dram_write_data_;");
-                pw.println("output         dram_write_data_push_;");
-                pw.println("input          dram_write_data_full;");
-                pw.println("input   [63:0] dram_read_data;");
-                pw.println("output         dram_read_data_pop_;");
-                pw.println("input          dram_read_data_empty;");
-                pw.println("input   [1:0]  dram_read_data_latency;");
+            for(PercolatedPort pp : sd.percolatedPorts) {
+                pw.print(pp.up ? "output" : "input");
+                pw.print("  ");
+                if (pp.width > 1)
+                    pw.print("["+(pp.width-1)+":0]");
+                pw.print(" ");
+                pw.print(pp.name);
+                pw.println(";");
             }
             if (filename.equals("ddr2")) {
                 pw.println("output  [31:0] ddr2_addr_;");

diff --git a/src/edu/berkeley/fleet/fpga/FpgaShip.java b/src/edu/berkeley/fleet/fpga/FpgaShip.java
index 87ba39f..332970e 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/FpgaShip.java
+++ b/src/edu/berkeley/fleet/fpga/FpgaShip.java
@@ -25,6 +25,8 @@ public class FpgaShip extends FleetTwoShip {
         }
         if (getType().toLowerCase().equals("debug"))
             module.createOutputPort("debug_out", getFleet().getWordWidth(), "");
+        for(PercolatedPort pp : sd.percolatedPorts)
+            this.module.percolatedPorts.add(pp);
     }
 
     public Iterator<Dock> iterator() { return (Iterator<Dock>)(Object)ports.values().iterator(); }

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index d24c2b4..17e447b 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -16,6 +16,17 @@ import static edu.berkeley.fleet.two.FleetTwoFleet.*;
 
 public class Verilog {
 
+    public static class PercolatedPort {
+        public final boolean up;
+        public final int width;
+        public final String name;
+        public PercolatedPort(String name, int width, boolean up) {
+            this.name = name;
+            this.width = width;
+            this.up = up;
+        }
+    }
+
     public static class SimpleValue implements Value {
         public final String s;
         public SimpleValue(String s) { this.s = s; }
@@ -153,6 +164,7 @@ public class Verilog {
         public Port getPort(String name) { return ports.get(name); }
 
         public HashSet<InstantiatedModule> instantiatedModules = new HashSet<InstantiatedModule>();
+        public LinkedList<PercolatedPort> percolatedPorts = new LinkedList<PercolatedPort>();
         public final ArrayList<Event> events = new ArrayList<Event>();
 
         // FIXME: always-alphabetical convention?
@@ -289,19 +301,8 @@ public class Verilog {
                 pw.println("  " + module.getName() + " " + getName() + "(clk, rst ");
                 for(String s : module.portorder)
                     pw.println(", " + getPort(s).getSimpleInterface());
-                if (module.name.equals("dram")) {
-                    pw.println("    , dram_addr");
-                    pw.println("    , dram_addr_r");
-                    pw.println("    , dram_addr_a");
-                    pw.println("    , dram_isread");
-                    pw.println("    , dram_write_data");
-                    pw.println("    , dram_write_data_push");
-                    pw.println("    , dram_write_data_full");
-                    pw.println("    , dram_read_data");
-                    pw.println("    , dram_read_data_pop");
-                    pw.println("    , dram_read_data_empty");
-                    pw.println("    , dram_read_data_latency");
-                }
+                for(PercolatedPort pp : module.percolatedPorts)
+                    pw.println("    , "+pp.name);
                 if (module.name.equals("ddr2")) {
                     pw.println("    , ddr2_addr");
                     pw.println("    , ddr2_addr_r");
@@ -491,18 +492,10 @@ public class Verilog {
                 Port p = ports.get(name);
                 pw.println("    , " + p.getInterface());
             }
+            for (InstantiatedModule im : this.instantiatedModules)
+                for(PercolatedPort pp : im.module.percolatedPorts)
+                    pw.println("    , "+pp.name);
             if (this.name.equals("root")) {
-                pw.println("    , dram_addr");
-                pw.println("    , dram_addr_r");
-                pw.println("    , dram_addr_a");
-                pw.println("    , dram_isread");
-                pw.println("    , dram_write_data");
-                pw.println("    , dram_write_data_push");
-                pw.println("    , dram_write_data_full");
-                pw.println("    , dram_read_data");
-                pw.println("    , dram_read_data_pop");
-                pw.println("    , dram_read_data_empty");
-                pw.println("    , dram_read_data_latency");
                 pw.println("    , vga_clk");
                 pw.println("    , vga_psave");
                 pw.println("    , vga_hsync");
@@ -529,18 +522,17 @@ public class Verilog {
             pw.println();
             pw.println("    input clk;");
             pw.println("    input rst;");
+            for (InstantiatedModule im : this.instantiatedModules)
+                for(PercolatedPort pp : im.module.percolatedPorts) {
+                    pw.print(pp.up ? "output" : "input");
+                    pw.print("  ");
+                    if (pp.width > 1)
+                        pw.print("["+(pp.width-1)+":0]");
+                    pw.print(" ");
+                    pw.print(pp.name);
+                    pw.println(";");
+                }
             if (this.name.equals("root")) {
-                pw.println("output  [31:0] dram_addr;");
-                pw.println("output         dram_addr_r;");
-                pw.println("input          dram_addr_a;");
-                pw.println("output         dram_isread;");
-                pw.println("output  [63:0] dram_write_data;");
-                pw.println("output         dram_write_data_push;");
-                pw.println("input          dram_write_data_full;");
-                pw.println("input   [63:0] dram_read_data;");
-                pw.println("output         dram_read_data_pop;");
-                pw.println("input          dram_read_data_empty;");
-                pw.println("input   [1:0]  dram_read_data_latency;");
                 pw.println("output  [31:0] ddr2_addr;");
                 pw.println("output         ddr2_addr_r;");
                 pw.println("input          ddr2_addr_a;");

diff --git a/src/edu/berkeley/fleet/two/ShipDescription.java b/src/edu/berkeley/fleet/two/ShipDescription.java
index dcf0a97..d1158ea 100644 (file)
--- a/src/edu/berkeley/fleet/two/ShipDescription.java
+++ b/src/edu/berkeley/fleet/two/ShipDescription.java
@@ -1,5 +1,6 @@
 package edu.berkeley.fleet.two;
 import edu.berkeley.fleet.api.*;
+import edu.berkeley.fleet.fpga.verilog.Verilog.PercolatedPort;
 import java.io.*;
 import java.util.*;
 
@@ -16,6 +17,8 @@ public class ShipDescription implements Iterable<DockDescription> {
     public DockDescription getDockDescription(String name) { return docks.get(name); }
     public Iterator<DockDescription> iterator() { return docks.values().iterator(); }
 
+    public final LinkedList<PercolatedPort> percolatedPorts = new LinkedList<PercolatedPort>();
+
     public ShipDescription(String name, BufferedReader r) throws IOException {
         if (name.endsWith(".ship")) name = name.substring(0, name.length()-".ship".length());
         this.name = name;
@@ -80,6 +83,16 @@ public class ShipDescription implements Iterable<DockDescription> {
                 else if (key.equals("data out"))  { inbox = false; }
                 else if (key.equals("in"))        { inbox = true;  }
                 else if (key.equals("out"))       { inbox = false; }
+                else if (key.startsWith("percolate")) { 
+                    key = s;
+                    key = key.substring("percolate".length()+1).trim();
+                    boolean up = key.startsWith("up");
+                    key = key.substring(key.indexOf(':')+1).trim();
+                    String name = key.substring(0, key.indexOf(' '));
+                    int width = Integer.parseInt(key.substring(key.indexOf(' ')).trim());
+                    percolatedPorts.add(new PercolatedPort(name, width, up));
+                    continue;
+                }
                 else if (key.startsWith("constant")) {
                     String constname = key.substring("constant".length()+1).trim();
                     String val       = s.substring(s.indexOf(':')+1).trim();