add rst wire (but do not do anything with it)

diff --git a/ships/Debug.ship b/ships/Debug.ship
index e1af16d..ba6bab1 100644 (file)
--- a/ships/Debug.ship
+++ b/ships/Debug.ship
@@ -31,9 +31,11 @@ public void service() {
 == FPGA ==============================================================
 `include "macros.v"
 
-module debug (clk, data_debug_data_r, data_debug_data_a, data_debug_data,
-                   data_debug_out_r, data_debug_out_a, data_debug_out );
+module debug (clk, rst,
+              data_debug_data_r, data_debug_data_a, data_debug_data,
+              data_debug_out_r, data_debug_out_a, data_debug_out );
   input clk;
+  input rst;
 
   input  data_debug_data_r;
   output data_debug_data_a;

diff --git a/ships/Memory.ship b/ships/Memory.ship
index e103fbd..bfe28c5 100644 (file)
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -167,8 +167,9 @@ sequence guarantee problem mentioned in the previous paragraph.
 `define BRAM_NAME some_bram
 
 /* bram.inc */
-module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo); 
+module `BRAM_NAME(clk, rst, we, a, dpra, di, spo, dpo); 
     input  clk; 
+    input  rst; 
     input  we; 
     input  [(`BRAM_ADDR_WIDTH-1):0] a; 
     input  [(`BRAM_ADDR_WIDTH-1):0] dpra; 
@@ -189,7 +190,7 @@ module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
 endmodule 
 /* bram.inc */
 
-module memory (clk, 
+module memory (clk, rst,
                cbd_r,          cbd_a_,         cbd_d,
                in_addr_r,      in_addr_a_,     in_addr_d,
                write_addr_r,   write_addr_a_,  write_addr_d,
@@ -203,6 +204,7 @@ module memory (clk,
               );
 
   input  clk;
+  input  rst;
   `input(in_addr_r,      in_addr_a,     in_addr_a_,     [(2+`DATAWIDTH-1):0],       in_addr_d)
   `input(write_addr_r,   write_addr_a,  write_addr_a_,  [(2+`DATAWIDTH-1):0],       write_addr_d)
   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
@@ -253,7 +255,7 @@ module memory (clk,
   reg launched;
   initial launched = 0;
 
-  some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
+  some_bram mybram(clk, rst, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
   assign out_d_ = ramread;
 
   always @(posedge clk) begin

diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java
index f5815a8..e4fafdf 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Fpga.java
+++ b/src/edu/berkeley/fleet/fpga/Fpga.java
@@ -121,9 +121,10 @@ public class Fpga extends Fleet {
 
         if (quiet) return;
         System.out.println("`include \"macros.v\"");
-        System.out.println("module fabric(clk, data_Memory0_command_r, data_Memory0_command_a, data_Memory0_command,");
+        System.out.println("module fabric(clk, rst, data_Memory0_command_r, data_Memory0_command_a, data_Memory0_command,");
         System.out.println("                   data_Debug0_out_r, data_Debug0_out_a, data_Debug0_out);");
         System.out.println("  input  clk;");
+        System.out.println("  input  rst;");
         System.out.println("  input  data_Memory0_command_r;");
         System.out.println("  output data_Memory0_command_a;");
         System.out.println("  output data_Debug0_out_r;");
@@ -161,7 +162,7 @@ public class Fpga extends Fleet {
             System.out.print(ship.getType().toLowerCase());
             System.out.print(" ");
             System.out.print("krunk"+(krunk++));
-            System.out.print("(clk, ");
+            System.out.print("(clk, rst, ");
             boolean first = true;
             for(Pump port : ship.getPumps()) {
                 if (!first) System.out.print(", ");
@@ -183,7 +184,7 @@ public class Fpga extends Fleet {
                 } else {
                     System.out.print("outbox");
                 }
-                System.out.print(" krunk"+(krunk++)+"(clk, ");
+                System.out.print(" krunk"+(krunk++)+"(clk, rst, ");
                 System.out.print("instruction_"+getUniqueName(port.getShip())+"_"+port.getName()+"_r, ");
                 System.out.print("instruction_"+getUniqueName(port.getShip())+"_"+port.getName()+"_a, ");
                 System.out.print("`packet_data(instruction_"+getUniqueName(port.getShip())+"_"+port.getName()+"), ");
@@ -202,11 +203,11 @@ public class Fpga extends Fleet {
 
         }
 
-        System.out.println("funnel ihornfun(clk,"+
+        System.out.println("funnel ihornfun(clk, rst, "+
                            "             ihornleft_r, ihornleft_a, ihornleft,"+
                            "             ihorn_r, ihorn_a, ihorn,"+
                            "             source_r, source_a, source);");
-        System.out.println("horn tophorn(clk,"+
+        System.out.println("horn tophorn(clk, rst, "+
                            "             ihornleft_r, ihornleft_a, ihornleft,"+
                            "             instruction_r, instruction_a, instruction,"+
                            "             dest_r, dest_a, dest);");
@@ -311,7 +312,7 @@ public class Fpga extends Fleet {
                 } else {
                     System.out.println("     "+indent+
                                        component+" "+
-                                       "krunk"+(krunk++)+"(clk, "+
+                                       "krunk"+(krunk++)+"(clk, rst, "+
                                        describe(prefix)+"_r, "+
                                        describe(prefix)+"_a, "+
                                        describe(prefix)+", "+
@@ -376,7 +377,7 @@ public class Fpga extends Fleet {
             if (auto) {
                 pw.println("`include \"macros.v\"");
                 pw.println();
-                pw.println("module " + filename + "( clk");
+                pw.println("module " + filename + "( clk, rst ");
                 for(PumpDescription bb : sd) {
                     String bb_name = bb.getName();
                     pw.print("        ");
@@ -394,6 +395,7 @@ public class Fpga extends Fleet {
                 pw.println("        );");
                 pw.println();
                 pw.println("    input clk;");
+                pw.println("    input rst;");
                 for(PumpDescription bb : sd) {
                     String bb_name = bb.getName();
                     pw.print("        ");

diff --git a/src/edu/berkeley/fleet/fpga/Generator.java b/src/edu/berkeley/fleet/fpga/Generator.java
index e0882f7..e0f9c6c 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Generator.java
+++ b/src/edu/berkeley/fleet/fpga/Generator.java
@@ -214,7 +214,7 @@ public class Generator {
                 instantiatedModules.add(this);
             }
             public void dump(PrintWriter pw) {
-                pw.println("  " + module.getName() + " " + getName() + "(clk");
+                pw.println("  " + module.getName() + " " + getName() + "(clk, rst ");
                 for(String s : module.portorder)
                     pw.println(", " + getPort(s).getSimpleInterface());
                 pw.println("   );");
@@ -327,7 +327,7 @@ public class Generator {
 
         public void dump(PrintWriter pw, boolean fix) {
             pw.println("`include \"macros.v\"");
-            pw.println("module "+name+"(clk");
+            pw.println("module "+name+"(clk, rst ");
             for(String name : portorder) {
                 Port p = ports.get(name);
                 pw.println("    , " + p.getInterface());
@@ -335,6 +335,7 @@ public class Generator {
             pw.println("   );");
             pw.println();
             pw.println("    input clk;");
+            pw.println("    input rst;");
             for(String name : ports.keySet()) {
                 Port p = ports.get(name);
                 pw.println("    " + p.getDeclaration());

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index e3ae759..505d6a7 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -91,7 +91,7 @@ module main
    wire root_out_r;
    wire [7:0] root_in_d;
 
-   root my_root(clk,
+   root my_root(clk, rst, 
                 root_in_r,  root_in_a,  root_in_d,
                 root_out_r, root_out_a, data_to_host);
 /*