\documentclass[10pt]{article}
\usepackage{palatino}
\usepackage{amsmath}
+\usepackage{pdflscape}
+\usepackage[figureright]{rotating}
\usepackage{epsfig}
\usepackage{color}
\usepackage{bytefield1}
\end{tabular}}
}
-\title{\vspace{-1cm}AM33: The FleetTwo Dock
+\title{\vspace{-1cm}AM33: The Marina Docks
\\
{\normalsize
Adam Megacz
\maketitle
\begin{abstract}
-Changes:
-
-\begin{tabular}{rl}
-\color{red}17-Feb\color{black}
-& \color{red} Clarified setting of the {\tt C}-flag\color{black}\\
-05-Jan
-& Fixed a one-word typo \\
-02-Jan
-& Added {\tt head} instruction \\
-& Lengthened external encoding of {\tt tail} instruction by one bit \\
-& Added {\tt abort} instruction \\
-& Removed {\tt OS} field from instructions \\
-& Renamed the {\tt Z}-flag (olc {\bf Z}ero) to the {\tt D}-flag (loop {\bf D}one)\\
-19-Dec
-& Updated diagram in section 3 to put dispatch path near MSB\\
-& Changed DP[37:25] to DP[37:27]\\
-& Added note on page 4 regarding previous\\
-14-Nov
-& Roll back ``Distinguish {\tt Z}-flag from OLC=0'' \\
-& Clarify what ``{\tt X-Extended}'' means \\
-& Change C-bit source selector from {\tt Di} to {\tt Dc} \\
-07-Nov
-& Distinguish {\tt Z}-flag from OLC=0\\
-& Add {\tt flush} instruction\\
-& Change {\t I} bit from ``Interruptable'' to ``Immune''\\
-20-Sep
-& Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\
-28-Aug
-& Note that decision to requeue is based on value of OLC {\it before} execution\\
-& Note that decision to open the hatch is based on value of {\tt OS} bit\\
+
+This document describes the Docks on the Marina test chip.
+
+%Changes:
+%
+%\begin{tabular}{rl}
+%29-Aug
+%& Final version \\
+%25-May
+%& Added errata for Kessels counter on Marina test chip \\
+%18-May
+%& Added errata for Marina test chip \\
+%17-Feb
+%& Clarified setting of the {\tt C}-flag\color{black}\\
+%& Removed {\tt OS} bit\color{black}\\
+%& Changed instruction length from 26 bits to 25\color{black}\\
+%& Updated which bits are used when the {\tt Path} latch captures from the data predecessor\color{black}\\
+%05-Jan
+%& Fixed a one-word typo \\
+%02-Jan
+%& Added {\tt head} instruction \\
+%& Lengthened external encoding of {\tt tail} instruction by one bit \\
+%& Added {\tt abort} instruction \\
+%& Removed {\tt OS} field from instructions \\
+%& Renamed the {\tt Z}-flag (olc {\bf Z}ero) to the {\tt D}-flag (loop {\bf D}one)\\
+%19-Dec
+%& Updated diagram in section 3 to put dispatch path near MSB\\
+%& Changed DP[37:25] to DP[37:27]\\
+%& Added note on page 4 regarding previous\\
+%14-Nov
+%& Roll back ``Distinguish {\tt Z}-flag from OLC=0'' \\
+%& Clarify what ``{\tt X-Extended}'' means \\
+%& Change C-bit source selector from {\tt Di} to {\tt Dc} \\
+%07-Nov
+%& Distinguish {\tt Z}-flag from OLC=0\\
+%& Add {\tt flush} instruction\\
+%& Change {\t I} bit from ``Interruptable'' to ``Immune''\\
+%20-Sep
+%& Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\
+%28-Aug
+%& Note that decision to requeue is based on value of OLC {\it before} execution\\
+%& Note that decision to open the hatch is based on value of {\tt OS} bit\\
%10-Jul
%& Added {\tt OLC=0} predicate \\
%& Eliminated {\tt TAPL} (made possible by previous change) \\
%& Created the {\tt Hold} field \\
%& Changed how ReLooping works \\
%& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
-\end{tabular}
+%\end{tabular}
\end{abstract}
\vfill
their destinations. Each dock has two destinations: one for {\it
instructions} and one for {\it data}. A Fleet is programmed by
depositing instruction packets into the switch fabric with paths that
-will lead them to instruction destinations of the docks at which they
+will lead them to the instruction destinations of the docks at which they
are to execute.
When a packet arrives at the instruction destination of a dock, it is
\pagebreak
-\section{The FleetTwo Dock}
+\section{The Marina Dock}
The diagram below represents a conceptual view of the interface
between ships and the switch fabric; actual implementation circuitry
instruction-width latches. The values in the instruction fifo control
the data latch. The dock also includes a {\it path latch}, which
stores the path along which outgoing packets will be
-sent.\color{black}
+sent.
Note that the instruction fifo in each dock has a destination of its
own; this is the {\it instruction destination} mentioned in the
the ``signal'' bit, and the routing of a packet is not affected by it;
the signal bit is used to pass control values between docks. Note that paths
terminating at an {\it instruction} destination need not have a signal
-bit. \color{black}
+bit.
\pagebreak
\section{Instructions}
sending it to the {\it instruction destination} of the dock at which
it is to execute.
-Each instruction is 26 bits long, which makes it possible for an
-instruction and an 11-bit path to fit in a single word of memory.
-This path is the path from the {\it dispatching} dock to the {\it
- executing} dock.
+There are two instruction formats, an {\it external format} described
+in this section and an {\it internal format} described in the last
+section of this memo.
+
+Each instruction is 25\color{black}\ bits long, which makes it
+possible for an instruction and an 12\color{black}-bit path to fit in
+a single word of memory. This path is the path from the {\it
+ dispatching} dock to the {\it executing} dock.
\vspace{0.5cm}
\setlength{\bitwidth}{3.5mm}
{\tt \footnotesize
\begin{bytefield}{37}
- \bitheader[b]{0,25,26,36}\\
- \bitbox{11}{dispatch path}
- \bitbox{26}{instruction}
+ \bitheader[b]{0,24,25,36}\\
+ \bitbox{12}{dispatch path}
+ \bitbox{25}{instruction (external format)}
\end{bytefield}}
\color{black}
-Note that the 11 bit {\tt dispatch path} field is not the same width
-as the 13 bit {\tt Immediate} path field in the {\tt move} instruction,
-which in turn may not be the same width as the actual path latches in
-the switch fabric.
-
-The algorithm for expanding a path to a wider width is specific to the
-switch fabric implementation, and is not specified by this
-document.\footnote{for the Marina experiment, the correct
- algorithm is to sign-extend the path; the most significant bit of
- the given path is used to fill all vacant bits of the latch} In
-particular, because the {\tt dispatch path} field is always used to
+Note that the 12\color{black}\ bit {\tt dispatch path} field is not
+the same width as the 13 bit {\tt Immediate} path field in the {\tt
+ move} instruction, which in turn may not be the same width as the
+actual path latches in the switch fabric. The algorithm for expanding
+a path to a wider width is specific to the switch fabric
+implementation, and may vary from Fleet to Fleet. For the Marina
+experiment, the correct algorithm is to sign-extend the path; the most
+significant bit of the given path is used to fill the vacant bit of
+the latch. Because the {\tt dispatch path} field is always used to
specify a path which terminates at an instruction destination (never a
data destination), and because instruction destinations ignore the
-signal bit, certain optimizations may be possible. \color{black}
-
+signal bit, certain optimizations may be possible.
%\subsection{Life Cycle of an Instruction}
%
%
\newcommand{\bitsHeader}{
\bitbox{1}{I}
- \bitbox{1}{}
\bitbox{3}{P}
}
\newcommand{\bitsHeaderNoI}{
- \bitbox{2}{}
+ \bitbox{1}{}
\bitbox{3}{P}
}
%
\end{itemize}
The {\tt OLC} applies to all instructions and can hold integers {\tt
- 0..MAX_OLC}.
+ 0..MAX_OLC} (63).
The {\tt ILC} applies only to {\tt move} instructions and can hold
-integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
+integers {\tt 0..MAX_ILC} (63) as well as a special value: $\infty$. When
{\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
executes until interrupted by a torpedo. After every {\tt move}
\begin{center}
\setlength{\bitwidth}{5mm}
{\tt{\footnotesize{
-\begin{bytefield}{26}
- \bitheader[b]{0,20,21,23-25}\\
+\begin{bytefield}{25}
+ \bitheader[b]{0,20,21,23-24}\\
\bitsHeaderNoI
\bitbox[tbr]{21}{}
\color{black}
\newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
{\tt
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{14-20}\\
\color{light}
\bitsHeader
\bitbox[l]{19}{}
\end{bytefield}}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{0,12,13}\\
- \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
+ \bitbox[1]{10}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
\bitbox[r]{1}{}
\bitbox{1}{\tt 1}
\bitbox{13}{\tt Immediate}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{11,12,13}\\
- \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:27\color{black}]\to Path}})\ \ }
+ \bitbox[1]{10}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:26\color{black}]\to Path}})\ \ }
\bitbox[r]{1}{}
\bitbox{1}{\tt 0}
\bitbox{1}{\tt 1}
\color{black}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{11,12,13}\\
- \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
+ \bitbox[1]{10}{\raggedleft {\tt move} ({\tt Path} unchanged):}
\bitbox[r]{1}{}
\bitbox{1}{\tt 0}
\bitbox{1}{\tt 0}
The {\tt I} bit stands for {\tt Immune}, and indicates if the
instruction is immune to torpedoes.
-Every time the {\tt move} instruction executes, the {\tt C} flag may
+Every time the {\tt move} instruction executes, the {\tt C} flag is
be set:
-\color{red}
\begin{itemize}
-\item At an {\it input} dock the {\tt C} flag is set to the signal bit
- of the incoming packet if {\tt Dc} bit is set. If the {\tt Dc}
- bit is not set the {\tt C} flag takes an unknown value.
-
-\item At an {\it output} dock the {\tt C} flag is set to a value
- provided by the ship if the {\tt Dc} bit is set. If the {\tt
- Dc} bit is not set, the {\tt C} flag is set to the signal bit of
- the incoming packet.
+\item If the dock is an {\it output} and the instruction has the {\tt
+ Dc} bit set, the {\tt C} flag is set to a value provided by the
+ ship.
+
+\item Otherwise, if {\tt Ti=1} at any kind of dock or {\tt Di=1} at an
+ input dock, the {\tt C} flag is set to the signal bit of the
+ incoming packet.
+
+\item Otherwise, the signal bit is set to an undefined value.
+
\end{itemize}
\color{black}
\newcommand{\bitsFlush}{\setlength{\bitwidth}{5mm}
{\tt
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{14-18}\\
- \bitbox[r]{7}{\raggedleft{\tt flush\ \ }}
+ \bitbox[r]{6}{\raggedleft{\tt flush\ \ }}
\bitbox{1}{\tt 0}
\color{black}
\bitbox{1}{\tt 0}
\newcommand{\bitsSet}{
{\tt
-\begin{bytefield}{26}
- \bitheader[b]{19-25}\\
+\begin{bytefield}{25}
+ \bitheader[b]{19-24}\\
\bitsHeaderNoI
\bitbox{1}{1}
\bitbox{1}{0}
\color{black}
\end{bytefield}}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{0,5,12-18}\\
\bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
\bitbox[r]{1}{}
\bitbox{6}{\tt Immediate}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{12-18}\\
\bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
\bitbox[r]{1}{}
\bitbox{12}{}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{12-18}\\
\bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
\bitbox[r]{1}{}
\bitbox{12}{}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{0,5,6,12-18}\\
\bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
\bitbox[r]{1}{}
\bitbox{6}{\tt Immediate}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{6,12-18}\\
\bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
\bitbox[r]{1}{}
\bitbox{6}{}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{12-18}\\
\bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
\bitbox[r]{1}{}
\bitbox{12}{}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{0,13-18}\\
\bitbox[1]{6}{\raggedleft \footnotesize {\tt Sign-Extended Immediate}\to{\tt Data Latch}}
\bitbox[r]{1}{}
\bitbox{14}{\tt Immediate}
\end{bytefield}
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{0,5,6,11,15-18}\\
\bitbox[1]{6}{\raggedleft {\tt Update Flags}}
\bitbox[r]{1}{}
}
\bitsSet
-The FleetTwo implementation is likely to have an unarchitected
+The Marina implementation has an unarchitected
``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
with the possibly-extended literal {\it at the time that the {\tt set}
instruction comes on deck}. This latch is then copied into the data
\newcommand{\bitsShift}{
\setlength{\bitwidth}{5mm}
{\tt
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{0,18-20}\\
\color{light}
\bitsHeaderNoI
}
\bitsShift
-The FleetTwo implementation is likely to have an unarchitected
+The Marina implementation has an unarchitected
``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
with the literal {\it at the time that the {\tt shift} instruction
comes on deck}. This latch is then copied into the data latch when
\subsection{{\tt abort}}
\newcommand{\bitsAbort}{\setlength{\bitwidth}{5mm}
{\tt
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{17-20}\\
\color{light}
\bitsHeaderNoI
\newcommand{\bitsHead}{
\setlength{\bitwidth}{5mm}
{\tt
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{17-20}\\
\color{light}
- \bitbox{5}{}
+ \bitbox{4}{}
\color{black}
\bitbox{1}{1}
\bitbox{1}{1}
\newcommand{\bitsTail}{
\setlength{\bitwidth}{5mm}
{\tt
-\begin{bytefield}{26}
+\begin{bytefield}{25}
\bitheader[b]{17-20}\\
\color{light}
- \bitbox{5}{}
+ \bitbox{4}{}
\color{black}
\bitbox{1}{1}
\bitbox{1}{1}
%
%\setlength{\bitwidth}{5mm}
%{\tt
-%\begin{bytefield}{26}
+%\begin{bytefield}{25}
% \bitheader[b]{16-19,21}\\
%\color{light}
% \bitbox{1}{A}
%
%\setlength{\bitwidth}{5mm}
%{\tt
-%\begin{bytefield}{26}
+%\begin{bytefield}{25}
% \bitheader[b]{16-19,21}\\
%\color{light}
% \bitbox{1}{A}
%%
%%\setlength{\bitwidth}{5mm}
%{\tt
-%\begin{bytefield}{26}
+%\begin{bytefield}{25}
% \bitheader[b]{0,5,16-19,21}\\
%\color{light}
% \bitbox{4}{}
%
%\setlength{\bitwidth}{5mm}
%{\tt
-%\begin{bytefield}{26}
+%\begin{bytefield}{25}
% \bitheader[b]{16-19,21}\\
%\color{light}
% \bitbox{4}{}
%
%\setlength{\bitwidth}{5mm}
%{\tt
-%\begin{bytefield}{26}
+%\begin{bytefield}{25}
% \bitheader[b]{16-19,21}\\
%\color{light}
% \bitbox{4}{}
%
%\setlength{\bitwidth}{5mm}
%{\tt
-%\begin{bytefield}{26}
+%\begin{bytefield}{25}
% \bitheader[b]{16-19,21}\\
%\color{light}
% \bitbox{4}{}
%clogged and whose instruction fifo contains no {\tt clog} instructions
%will cause the dock to deadlock.
+\pagebreak
+\section*{Errata}
+
+The following additional restrictions have been imposed on the dock in
+the Marina test chip:
+
+\subsection*{Both Docks}
+
+\begin{enumerate}
+
+\item
+A Marina dock initializes with the {\tt ILC}, {\tt OLC}, and flags in
+an indeterminate state.
+
+\item
+The instruction immediately after a {\tt move} instruction must not be
+a {\tt set flags} instruction which utilizes the {\tt C}-flag (the
+value of the {\tt C}-flag is not stable for a brief time after a {\tt
+ move}).
+
+\item
+If a {\tt move} instruction is torpedoable (ie it has the {\tt I} bit
+set to {\tt 0}), it {\it must} have either the {\tt Ti} bit or {\tt
+ Di} bit set (or both). It is not permitted for a torpedoable {\tt
+ move} to have both bits cleared.
+
+\end{enumerate}
+
+
+\subsection*{Dock with Ivan's Counter (non-stretch)}
+
+\begin{enumerate}
+
+\item
+
+A torpedoable {\tt move} instruction must not be followed immediately
+by a {\tt set olc} instruction or another torpedoable {\tt move}.
+
+\item
+
+This document specifies that when a torpedoable {\tt move} instruction
+executes successfully, the {\tt D} flag is unchanged. In Marina, when
+a torpedoable {\tt move} instruction executes successfully, it causes
+the {\tt D} flag to be set if the {\tt OLC} was zero and causes it to
+be cleared if the {\tt OLC} was nonzero. Thus, in the following
+instruction sequence:
+
+ \begin{verbatim}
+ head;
+ [*] set olc=1;
+ send token to self:i;
+ [T] recv token;
+ [*] send token to self;
+ [T] recv token;
+ [*] abort;
+ tail;
+ \end{verbatim}
+Will leave the {\tt D} flag {\it set} on Marina, whereas a strict
+implementation of this document would leave it cleared.
+
+In practice, this distinction rarely matters.
+
+\end{enumerate}
+
+\subsection*{Dock with Kessels Counter (``stretch'')}
+
+With the Kessels counter, the {\tt D}-flag {\it is exactly equal to}
+the zeroness of the {\tt OLC}; it cannot be ``out of sync'' with it.
+
+\begin{enumerate}
+
+\item
+Every ``load OLC'' instruction must be predicated on the {\tt D}-flag
+being {\it set}. This is a sneaky way of forcing the programmer to
+``run down'' the counter before loading it, because Kessels' counter
+does not support ``unloading.''
+
+\item
+Every ``decrement OLC'' instruction must be predicated on the {\tt
+ D}-flag being {\it cleared}. This way we never have to check if the
+counter is already empty before decrementing.
+
+\item
+The instruction after a torpedoable {\tt move} must not be predicated
+on the {\tt D}-flag being {\it set} (it may be predicated on the {\tt
+ D}-flag being {\it cleared}. This is because, while the move
+instruction is waiting to execute, the {\tt D}-flag will be cleared,
+and the predicate stage believes that it can skip the instruction even
+though {\tt do[ins]} is still high (I think this is dumb).
+
+
+\end{enumerate}
+
+\color{black}
\pagebreak
-\section*{Instruction Encoding Map\color{black}}
+\section*{External Instruction Encoding Map\color{black}}
\vspace{3mm}\hspace{-1cm}{\tt shift}\hspace{1cm}\vspace{-6mm}\\
%\pagebreak
%\epsfig{file=best,height=5in,angle=90}
+\pagebreak
+\section*{Internal Instruction Encoding Map\color{black}}
+
+Marina Instructions in main memory occupy 37 bits. Of this, 11 bits
+give the path to the dock which is to execute the instruction; thus,
+only 26 of these bits are interpreted by the dock.
+
+It is easiest to design the OD and EX stages of the dock if the
+control bits supplied there are mostly one-hot encoded. Moreover, due
+to layout considerations there is very little cost associated with
+making the instruction fifo 36 bits wide rather than 26 bits wide.
+
+Due to these two considerations, all 26-bit instructions
+binary-coded-control instructions are expanded into 36-bit
+unary-coded-control instructions upon entry to the instruction fifo.
+This section documents the 36-bit unary-coded-control format.
+
+\subsection*{Predicate Field}
+
+The {\tt Predicate} field, common to many instructions, consists of a
+six-bit wide, one-hot encoded field. The instruction will be {\bf
+ skipped} (not executed) if {\bf any} condition corresponding to a
+bit whose value is one is met.
+
+\setlength{\bitwidth}{3.5mm}
+{\footnotesize\tt\begin{bytefield}{36}
+ \bitheader[b]{0,29-35}\\
+\color{black}
+ \bitbox{1}{D}
+ \bitbox{1}{!D}
+ \bitbox{1}{!B}
+ \bitbox{1}{B}
+ \bitbox{1}{!A}
+ \bitbox{1}{A}
+\color{light}
+ \bitbox{30}{}
+\end{bytefield}}
+
+For example, if bits 31 and 34 are set, the instruction will be
+skipped if either the {\tt B} flag is cleared or the {\tt A} flag is
+set. Equivalently, it will be executed iff the {\tt B} flag is set
+and the {\tt A} flag is cleared.
+
+\subsection*{Set Flags}
+
+Each of the {\tt FlagA} and {\tt FlagB} fields in the Set Flags
+instruction gives a truth table; the new value of the flag is the
+logical OR of the inputs whose bits are set to {\tt 1}.
+
+\setlength{\bitwidth}{5mm}
+{\tt\begin{bytefield}{6}
+ \bitheader[b]{0-5}\\
+\color{black}
+ \bitbox{1}{!C}
+ \bitbox{1}{C}
+ \bitbox{1}{!B}
+ \bitbox{1}{B}
+ \bitbox{1}{!A}
+ \bitbox{1}{A}
+\end{bytefield}}
+
+\newcommand{\common}{%
+\bitbox{6}{Predicate}%
+}
+
+\pagebreak
+\pagestyle{plain}
+\pdfpagewidth 8.5in
+\pdfpageheight 11in
+\textheight 7.9in
+\textwidth 7.0in
+\oddsidemargin 0.9in
+%\headwidth 6.0in
+
+\begin{sidewaysfigure}[h!]
+%\begin{landscape}
+
+\setlength{\bitwidth}{5mm}
+\begin{tabular}{lr}
+\\
+Shift &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,18,19,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+ \bitbox{19}{immediate}
+\end{bytefield}} \\
+Set Data Latch &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,13,14,15,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{0}
+\color{light}
+ \bitbox{4}{}
+\color{black}
+ \bitbox{1}{+-}
+ \bitbox{14}{immediate to sign ext}
+\end{bytefield}} \\\hline
+\\
+Move, Immediate$\rightarrow$Path &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,13,14-20,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{Tp}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{rD}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{Ti}
+ \bitbox{1}{Di}
+ \bitbox{1}{Dc}
+ \bitbox{1}{Do}
+ \bitbox{1}{To}
+ \bitbox{1}{1}
+ \bitbox{13}{Immediate}
+\end{bytefield}} \\
+Move, DP[37:26]$\rightarrow$Path &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,12-13,14-20,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{Tp}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{rD}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{Ti}
+ \bitbox{1}{Di}
+ \bitbox{1}{Dc}
+ \bitbox{1}{Do}
+ \bitbox{1}{To}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+\color{light}
+ \bitbox{12}{}
+\end{bytefield}} \\
+Move, Path unchanged &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,11-13,14-20,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{Tp}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{rD}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{Ti}
+ \bitbox{1}{Di}
+ \bitbox{1}{Dc}
+ \bitbox{1}{Do}
+ \bitbox{1}{To}
+ \bitbox{1}{0}
+ \bitbox{1}{1}
+ \bitbox{1}{F$\dagger$}
+\color{light}
+ \bitbox{11}{}
+\end{bytefield}} \\
+\hline
+\color{black}
+\\
+Set Flags &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,11,12,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{9}{}
+\color{black}
+ \bitbox{6}{FlagB}
+ \bitbox{6}{FlagA}
+\end{bytefield}} \\\hline
+\\
+Decrement OLC &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,20-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{20}{}
+\color{black}
+\end{bytefield}} \\
+Data Latch\to OLC &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,19-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{19}{}
+\color{black}
+\end{bytefield}} \\
+Immediate\to OLC &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,5,19-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+\color{black}
+ \bitbox{1}{{0}}
+\color{light}
+ \bitbox{13}{}
+\color{black}
+ \bitbox{6}{Immediate}
+\end{bytefield}} \\\hline
+\\
+Data Latch\to ILC &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,19,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{0}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{19}{}
+\color{black}
+\end{bytefield}} \\
+Immediate\to ILC &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,5,7,19,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+\color{light}
+ \bitbox{10}{}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{0${}^\star$}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{6}{Immediate}
+\end{bytefield}} \\
+$\infty$\to ILC &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{0,7,21-30,35}\\
+\common
+\color{light}
+ \bitbox{3}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{0}
+\color{light}
+ \bitbox{11}{}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1${}^\star$}
+\color{light}
+ \bitbox{1}{}
+\color{light}
+ \bitbox{6}{}
+\end{bytefield}} \\\hline
+\\
+{\tt head} &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{29}\\
+\color{light}
+ \bitbox{6}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{2}{}
+\color{light}
+ \bitbox{27}{}
+\end{bytefield}} \\
+{\tt abort${}^1$} &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{28}\\
+\color{black}
+ \bitbox{6}{Predicate}
+\color{light}
+ \bitbox{1}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{6}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{9}{}
+\color{black}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+ \bitbox{1}{1}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+ \bitbox{1}{0}
+ \bitbox{1}{1}
+\end{bytefield}} \\
+{\tt tail} &
+{\tt\begin{bytefield}{36}
+ \bitheader[b]{27}\\
+\color{light}
+ \bitbox{6}{}
+\color{light}
+ \bitbox{2}{}
+\color{black}
+ \bitbox{1}{1}
+\color{light}
+ \bitbox{27}{}
+\end{bytefield}} \\
+\\
+\end{tabular}
+$\star$ -- Bit 8 is the ``infinity'' bit \\
+$\dagger$ -- When a ``Move, Path unchanged'' is performed, bit 12 is copied to the ``flushing latch''. \\
+.\hspace{0.5cm} When a ship fires, it examines the ``flushing latches'' of all of its inboxes as part of its decision about what to do. \\
+$1$ -- The encoding of the {\tt abort} instruction was chosen in order to make it look like a {\tt set flags} instruction which does not change the flags. \\
+Tp\ \ = Torpedoable (1=Torpedoable, 0=Not-Torpedoable) \\
+rD\ \ = recompute D-flag (1=recompute, 0=leave unchanged)
+%\end{landscape}
+\end{sidewaysfigure}
+
+\pagebreak
+\section*{Marina Dock Block Diagram}
+This diagram was produced by Ivan Sutherland.
+\\
+\epsfig{file=blockDiagram,width=8in,angle=90}
\end{document}
projects / fleet.git / commitdiff