added Alex's ESD experiment (LVS fixes)

diff --git a/electric/esdTest.jelib b/electric/esdTest.jelib
index 365a786..938a676 100644 (file)
--- a/electric/esdTest.jelib
+++ b/electric/esdTest.jelib
@@ -28,33 +28,25 @@ Tnmos|CapacitanceParasiticForDiffusionINnmos()D0.10000000149011612|CapacitancePa
 Trcmos|ScaleFORrcmos()D1000.0
 
 # Cell esdTopFilled;1{ic}
-CesdTopFilled;1{ic}||artwork|1243544400420|1243586774777|E
+CesdTopFilled;1{ic}||artwork|1243544400420|1243617261788|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOpened-Thicker-Polygon|art@1||0|0|8|10|||SCHEM_function(D5G2;)SesdTopFilled|trace()V[-4/-5,-4/5,4/5,4/-5,-4/-5]
-Nschematic:Bus_Pin|pin@0||3|7||||
-Nschematic:Wire_Pin|pin@1||3|5||||
 Nschematic:Bus_Pin|pin@2||-6|0||||
 Ngeneric:Invisible-Pin|pin@3||-4|0|1|1||
 Nschematic:Bus_Pin|pin@4||6|0||||
 Ngeneric:Invisible-Pin|pin@5||4|0|1|1||
-Nschematic:Bus_Pin|pin@6||0|7||||
-Nschematic:Wire_Pin|pin@7||0|5||||
 Nschematic:Bus_Pin|pin@10||-3|7||||
 Nschematic:Wire_Pin|pin@11||-3|5||||
-Aschematic:wire|net@0|||2700|pin@1||3|5|pin@0||3|7
 Aschematic:bus|net@1|||IJ0|pin@3||-4|0|pin@2||-6|0
 Aschematic:bus|net@2|||IJ1800|pin@5||4|0|pin@4||6|0
-Aschematic:wire|net@3|||2700|pin@7||0|5|pin@6||0|7
 Aschematic:wire|net@5|||2700|pin@11||-3|5|pin@10||-3|7
-Egnd||D5G2;|pin@0||B
 Ein[0:2]||D5G2;|pin@2||I
 Eout[0:2]||D5G2;|pin@4||O
-Evdd||D5G2;|pin@6||B
 EvddAlex||D5G2;|pin@10||I
 X
 
 # Cell esdTopFilled;1{lay}
-CesdTopFilled;1{lay}||cmos90|1239558882952|1243586905416|
+CesdTopFilled;1{lay}||cmos90|1239558882952|1243619263399||ATTR_NCC(D5G50;NTX748.5;Y-763.5;)S["exportsConnectedByParent gnd /gnd_[0-9]+/"]
 Ngeneric:Facet-Center|art@0||0|0||||AV
 IfillM:fillAll1x9vdd;1{lay}|fillAll1@6||-4896|-5616|||D5G4;
 IfillM:fillAll1x9vdd;1{lay}|fillAll1@7||-3456|-5616|||D5G4;
@@ -1787,6 +1779,13 @@ Egnd_1478||D5G5;|fillAll9@251|gnd_5|G
 Egnd_1479||D5G5;|fillAll9@251|gnd_7|G
 Egnd_1480||D5G5;|fillAll9@254|gnd_5|G
 Egnd_1481||D5G5;|fillAll9@254|gnd_7|G
+Egnd_1482||D5G25;|top@1|gnd|G
+Ein[0]||D5G2;|top@1|in[0]|I
+Ein[1]||D5G2;|top@1|in[1]|I
+Ein[2]||D5G2;|top@1|in[2]|I
+Eout[0]||D5G2;|top@1|out[0]|O
+Eout[1]||D5G2;|top@1|out[1]|O
+Eout[2]||D5G2;|top@1|out[2]|O
 Evdd||D5G5;|fillAll1@40|vdd|P
 EvddAlex||D5G25;|top@1|vdd|I
 Evdd_1||D5G5;|fillAll1@6|vdd_1|P
@@ -2917,34 +2916,26 @@ Evdd_1487||D5G5;|fillAll9@254|vdd_23|P
 X
 
 # Cell esdTopFilled;1{sch}
-CesdTopFilled;1{sch}||schematic|1243544323286|1243586716447|
+CesdTopFilled;1{sch}||schematic|1243544323286|1243619136090|
 Ngeneric:Facet-Center|art@0||0|0||||AV
-NOff-Page|conn@0||35.5|16.5|||R|
-NOff-Page|conn@2||33.5|18|||R|
 NOff-Page|conn@3||-8.5|4||||
 NOff-Page|conn@4||10.5|4||||
-NGlobal-Partition|conn@5||0.5|21.5||||
+NOff-Page|conn@6||2.5|22|||RRR|
 IesdTopFilled;1{ic}|esdTopFi@0||22.5|19.5|||D5G4;
 IfillM:fillCap;1{ic}|fillCap[1:6786]|D5G1;|33.5|4.5|||D5G4;
+NGround|gnd@1||0.5|16.5|||Y|
 NWire_Pin|pin@0||-1.5|18||||
 Ngeneric:Invisible-Pin|pin@1||-11|15|||||ART_message(D5G1;)S[This vdd18 is NOT connected,to the one for the marina,"padframe, so it is not",exported above this level]
-Ngeneric:Invisible-Pin|pin@2||33|-4|||||ART_message(D5G1;)S[This fillCap iS connected,to the rest of the fill in the,"core, so the vdd/gnd ports",are what really goes here]
-NWire_Pin|pin@3||35.5|11||||
-NWire_Pin|pin@4||33.5|11||||
-NWire_Pin|pin@5||2.5|18||||
+Ngeneric:Invisible-Pin|pin@2||33|-4|||||ART_message(D5G1;)S[This fillCap iS connected,to the rest of the fill in the,"core, so the vdd/gnd globals",are what really goes here]
 Itop;1{ic}|top@0||0.5|4|||D5G4;
-Awire|gnd|D5G1;||2700|top@0|gnd|2.5|11|pin@5||2.5|18
 Abus|net@3|||IJ0|conn@4|a|8.5|4|top@0|out[0:2]|5.5|4
 Abus|net@4|||IJ1800|conn@3|y|-6.5|4|top@0|in[0:2]|-4.5|4
-Awire|net@6|||900|conn@0|a|35.5|14.5|pin@3||35.5|11
-Awire|net@7|||900|conn@2|a|33.5|16|pin@4||33.5|11
-Awire|net@9|||900|conn@5|bottom|0.5|20.5|top@0|vdd|0.5|11
+Awire|net@15|||900|gnd@1||0.5|14.5|top@0|gnd|0.5|11
+Awire|net@16|||2700|top@0|vddAlex|2.5|11|conn@6|y|2.5|20
 Awire|vdd18|D5G1;||2700|top@0|vdd18|-1.5|11|pin@0||-1.5|18
-Egnd||D5G2;X1;|conn@0|y|B
 Ein[0:2]||D5G2;X-8;|conn@3|y|I
 Eout[0:2]||D5G2;X4.5;|conn@4|y|O
-Evdd||D5G2;X2;|conn@2|y|B
-EvddAlex||D5G2;|conn@5|top|I
+EvddAlex||D5G2;|conn@6|a|I
 X
 
 # Cell fork_halfUm;1{lay}
@@ -3459,33 +3450,33 @@ Eio_1||D5G2;|pin@33||B
 X
 
 # Cell top;1{ic}
-Ctop;1{ic}||artwork|1243544111290|1243544111297|E
+Ctop;1{ic}||artwork|1243544111290|1243618979480|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOpened-Thicker-Polygon|art@1||0|0|6|10|||SCHEM_function(D5G2;)Stop|trace()V[-3/-5,-3/5,3/5,3/-5,-3/-5]
-Nschematic:Bus_Pin|pin@0||2|7||||
-Nschematic:Wire_Pin|pin@1||2|5||||
 Nschematic:Bus_Pin|pin@2||-5|0||||
 Ngeneric:Invisible-Pin|pin@3||-3|0|1|1||
 Nschematic:Bus_Pin|pin@4||5|0||||
 Ngeneric:Invisible-Pin|pin@5||3|0|1|1||
-Nschematic:Bus_Pin|pin@6||0|7||||
-Nschematic:Wire_Pin|pin@7||0|5||||
 Nschematic:Bus_Pin|pin@8||-2|7||||
 Nschematic:Wire_Pin|pin@9||-2|5||||
-Aschematic:wire|net@0|||2700|pin@1||2|5|pin@0||2|7
+Nschematic:Bus_Pin|pin@10||2|7|||RRR|
+Nschematic:Wire_Pin|pin@11||2|5|||RRR|
+Nschematic:Bus_Pin|pin@12||0|7|||RRR|
+Nschematic:Wire_Pin|pin@13||0|5|||RRR|
 Aschematic:bus|net@1|||IJ0|pin@3||-3|0|pin@2||-5|0
 Aschematic:bus|net@2|||IJ1800|pin@5||3|0|pin@4||5|0
-Aschematic:wire|net@3|||2700|pin@7||0|5|pin@6||0|7
 Aschematic:wire|net@4|||2700|pin@9||-2|5|pin@8||-2|7
-Egnd||D5G2;|pin@0||B
+Aschematic:wire|net@5|||2700|pin@11||2|5|pin@10||2|7
+Aschematic:wire|net@6|||2700|pin@13||0|5|pin@12||0|7
+Egnd||D5G2;|pin@12||I
 Ein[0:2]||D5G2;|pin@2||I
 Eout[0:2]||D5G2;|pin@4||O
-Evdd||D5G2;|pin@6||B
 Evdd18||D5G2;|pin@8||B
+EvddAlex||D5G2;|pin@10||I
 X
 
 # Cell top;1{lay}
-Ctop;1{lay}||cmos90|1241731339694|1243383593144|
+Ctop;1{lay}||cmos90|1241731339694|1243617566249|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NX-Metal-2-Metal-3-Con|contact@0||236|7680|37.2|21.2||
 NX-Metal-2-Metal-3-Con|contact@1||4556|7680|37.2|21.2||
@@ -4217,18 +4208,18 @@ Ein[2]||D5G2;|pad_inpu@2|in|I
 Eout[0]||D5G2;|pad_anal@3|analog_io|O
 Eout[1]||D5G2;|pad_anal@0|analog_io|O
 Eout[2]||D5G2;|pad_anal@1|analog_io|O
-Evdd||D5G2;|pad_anal@0|VDD|P
 Evdd18||D5G2;|pad_inpu@0|vdd18|I
+Evdd|vddAlex|D5G2;|pad_anal@0|VDD|P
 X
 
 # Cell top;1{sch}
-Ctop;1{sch}||schematic|1241731410575|1243544118479|
+Ctop;1{sch}||schematic|1241731410575|1243618420202|
 Ngeneric:Facet-Center|art@0||0|0||||AV
-NOff-Page|conn@0||30|-20||||
 NOff-Page|conn@1||30|-15||||
-NOff-Page|conn@2||30|-10||||
 NOff-Page|conn@3||-65|-1||||
 NOff-Page|conn@4||7|-1||||
+NOff-Page|conn@6||-85.5|17||||
+NOff-Page|conn@7||-84.5|-11|||X|
 Ipadframe_r3:fill_split_cap_vdd;1{ic}|fillcap[1:669]|D5G1;|1|-56.5|||D5G4;
 Ipadframe_r3:pad_analog_no_esd;1{ic}|pad_anal@0||-17|1|||D5G4;
 Ipadframe_r3:pad_analog_no_esd;1{ic}|pad_anal@1||-17|-28.5|||D5G4;
@@ -4271,6 +4262,8 @@ NWire_Pin|pin@34||-23|-67.5||||
 NWire_Pin|pin@35||-37|-67.5||||
 NWire_Pin|pin@36||3|-67||||
 NWire_Pin|pin@37||3|-52.5||||
+NWire_Pin|pin@39||-65.5|17||||
+NWire_Pin|pin@40||-68|-11||||
 Itop;1{ic}|top@0||33.5|32.5|||D5G4;
 Awire|gnd|D5G1;||900|pad_anal@0|VSS|-11|-7|pin@2||-11|-14
 Awire|gnd|D5G1;||900|pad_inpu@0|gnd|-33.5|-7.5|pin@3||-33.5|-14
@@ -4282,6 +4275,7 @@ Awire|gnd|D5G1;||2700|pin@33||-9|-67.5|pad_vdd1@0|gnd|-9|-65.5|EDIF_name()Sgnd
 Awire|gnd|D5G1;||2700|pin@34||-23|-67.5|pad_vdd@0|gnd|-23|-65.5|EDIF_name()Sgnd
 Awire|gnd|D5G1;||2700|pin@35||-37|-67.5|pad_gnd@1|gnd|-37|-65.5|EDIF_name()Sgnd
 Awire|gnd|D5G1;||900|fillcap[1:669]|gnd|3|-63.5|pin@36||3|-67
+Awire|gnd|D5G1;||1800|conn@7|a|-82.5|-11|pin@40||-68|-11
 Awire|in[0]|D5G1;||1800|pin@18||-53|28.5|pad_inpu@3|in|-44|28.5
 Awire|in[1]|D5G1;||1800|pin@22||-53|-1|pad_inpu@0|in|-44|-1
 Awire|in[2]|D5G1;||1800|pin@26||-53|-30.5|pad_inpu@2|in|-44|-30.5
@@ -4299,14 +4293,15 @@ Awire|vdd|D5G1;||2700|pad_inpu@3|vdd|-32|34.5|pin@16||-32|41
 Awire|vdd|D5G1;||2700|pad_anal@2|VDD|-11|35.5|pin@17||-11|41
 Awire|vdd|D5G1;||2700|pad_vdd@0|vdd|-23|-54.5|pin@32||-23|-52.5|EDIF_name()Svdd
 Awire|vdd|D5G1;||2700|fillcap[1:669]|vdd|3|-57.5|pin@37||3|-52.5
+Awire|vdd|D5G1;||1800|conn@6|y|-83.5|17|pin@39||-65.5|17
 Awire|vdd18|D5G1;||2700|pad_inpu@0|vdd18|-33.5|5|pin@4||-33.5|14
 Awire|vdd18|D5G1;||2700|pad_inpu@2|vdd18|-33.5|-24.5|pin@9||-33.5|-15.5
 Awire|vdd18|D5G1;||2700|pad_inpu@3|vdd18|-33.5|34.5|pin@15||-33.5|43.5
 Awire|vdd18|D5G1;||2700|pad_gnd@1|vdd18|-37|-54.5|pin@30||-37|-52.5|EDIF_name()Svdd18
 Awire|vdd18|D5G1;||2700|pad_vdd1@0|vdd18|-9|-54.5|pin@31||-9|-52.5|EDIF_name()Svdd18
-Egnd||D5G2;X2;|conn@0|y|B
+Egnd||D5G2;|conn@7|y|I
 Evdd_1|in[0:2]|D5G2;X-8;|conn@3|y|I
 Eout[0:2]||D5G2;X4.5;|conn@4|y|O
-Evdd||D5G2;X2;|conn@2|y|B
 Evdd18||D5G2;X3.5;|conn@1|y|B
+EvddAlex||D5G2;|conn@6|a|I
 X

diff --git a/electric/marina_padframe.delib/marinaPadframe.lay b/electric/marina_padframe.delib/marinaPadframe.lay
index 191ba4f..f664d0a 100644 (file)
--- a/electric/marina_padframe.delib/marinaPadframe.lay
+++ b/electric/marina_padframe.delib/marinaPadframe.lay
@@ -9,7 +9,7 @@ LedgesM|edgesM
 LesdTest|esdTest
 
 # Cell marinaPadframe;1{lay}
-CmarinaPadframe;1{lay}||cmos90|1185513012222|1243586445537|I
+CmarinaPadframe;1{lay}||cmos90|1185513012222|1243631009152|I|ATTR_NCC(D5G127;NT)S["exportsConnectedByParent gnd /gnd_[0-9]+/"]
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NX-Metal-2-Metal-3-Con|contact@0||-20863|-17377|7.2|7.2||
 NX-Metal-2-Metal-3-Con|contact@1||-20863|2592|7.2|7.2||
@@ -2632,6 +2632,7 @@ EcrosserTap2||D5G127;|pads_sou@0|VDD_20|O
 EdukeTap||D5G127;|pads_sou@3|VDD|O
 Egnd||D5G127;|pads_sou@0|VSS|G
 EVSS_3|gnd_1|D5G127;|pads_sou@3|VSS_3|B
+Egnd_1482||D5G25;|esdTopFi@0|gnd_1482|G
 Egnd_sense||D5G127;|pads_sou@2|VSS_31|G
 EinfinityTap1||D5G127;|pads_sou@1|pad_bond@645451572|O
 EinfinityTap2||D5G127;|pads_sou@1|VSS|O
@@ -2640,6 +2641,7 @@ Eloop_out||D5G127;|pads_sou@1|VSS_9|O
 Emc||D5G127;|pads_sou@0|VDD_9|I
 EringTap||D5G127;|pads_sou@0|VDDPST18_3|O
 Evdd||D5G127;|pads_sou@0|VDD|P
+EvddAlex||D5G25;|esdTopFi@0|vddAlex|I
 EVDD_8|vdd_1|D5G127;|pads_sou@3|VDD_8|P
 Evdd_sense||D5G127;|pads_sou@2|VDD_31|P
 X

diff --git a/electric/marina_padframe.delib/marinaPadframe.sch b/electric/marina_padframe.delib/marinaPadframe.sch
index 56587cc..79be42c 100755 (executable)
--- a/electric/marina_padframe.delib/marinaPadframe.sch
+++ b/electric/marina_padframe.delib/marinaPadframe.sch
@@ -9,7 +9,7 @@ LedgesM|edgesM
 LesdTest|esdTest
 
 # Cell marinaPadframe;2{sch}
-CmarinaPadframe;2{sch}||schematic|1185925856743|1243586825450|I
+CmarinaPadframe;2{sch}||schematic|1185925856743|1243619341564|I
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||69|-35.5||||
 NOff-Page|conn@1||69|-38.5||||
@@ -32,8 +32,8 @@ NOff-Page|conn@19||-66|-9||||
 NOff-Page|conn@21||-66|15|||X|
 NOff-Page|conn@22||-64|-35.5|||X|
 NOff-Page|conn@25||-66|9|||RR|
-NOff-Page|conn@26||24|51|||RRR|
-IesdTest:esdTopFilled;1{ic}|esdTopFi@0||27|19|||D5G4;
+NOff-Page|conn@26||24|30.5|||RRR|
+IesdTest:esdTopFilled;1{ic}|esdTopFi@0||27|18.5|||D5G4;
 IedgesM:filledFrame;1{ic}|filledFr@0||23|-21|||D5G4;
 NGround|gnd@2||34.5|-19||||
 NGround|gnd@3||-35|29||||
@@ -202,10 +202,8 @@ Awire|net@244|||0|pin@95||-35|36.5|pin@18||-43|36.5
 Awire|net@245|||2700|gnd@3||-35|31|pin@95||-35|36.5
 Awire|net@246|||1800|pin@8||43.5|-38.5|conn@1|a|67|-38.5
 Awire|net@247|||0|pin@97||27|33.5|pads_north|VDD|21|33.5
-Awire|net@248|||2700|esdTopFi@0|vdd|27|26|pin@97||27|33.5
 Awire|net@249|||1800|pads_north|VSS|21|36.5|pin@98||30|36.5
-Awire|net@250|||2700|esdTopFi@0|gnd|30|26|pin@98||30|36.5
-Awire|net@251|||900|conn@26|y|24|49|esdTopFi@0|vddAlex|24|26
+Awire|net@251|||900|conn@26|y|24|28.5|esdTopFi@0|vddAlex|24|25.5
 ETCK||D4G2;|conn@16|a|I
 ETDI||D4G2;|conn@17|a|I
 ETDO||D6G2;|conn@25|y|O