try to re-enable break line in Debug.ship (but doesnt work), add a note about deadlock

diff --git a/ships/Debug.ship b/ships/Debug.ship
index 861e66c..7b4c7b6 100644 (file)
--- a/ships/Debug.ship
+++ b/ships/Debug.ship
@@ -63,7 +63,7 @@ public void service() {
   wire break;
   wire uart_cts;
   assign uart_cts = 0;
-  assign rst_out = rst_in || (force_reset!=0);
+  assign rst_out = rst_in || (force_reset!=0) || break;
 
   // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
   // using a 33Mhz clock,
@@ -91,7 +91,7 @@ public void service() {
 
    // fpga -> host
    always @(posedge clk) begin
-     if (rst_in) begin
+     if (rst_in || break) begin
        count_in    <= 0;
        count_out   <= 0;
        force_reset <= 0;
@@ -128,6 +128,11 @@ public void service() {
        data_to_fleet_read_enable <= 0;
        if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
 
+         // Note: if the switch fabric refuses to accept a new item,
+         // we can get deadlocked in a state where sending a reset
+         // code (2'b11) won't have any effect.  Probably need to go
+         // back to using the break signal.
+
            // command 0: data
          if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
            data_to_fleet_read_enable <= 1;