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raw | patch | inline | side by side (parent: 879217e)
move ucf constraints into .ship files
authormegacz <adam@megacz.com>
Sat, 7 Mar 2009 22:16:02 +0000 (14:16 -0800)
committermegacz <adam@megacz.com>
Sat, 7 Mar 2009 22:16:02 +0000 (14:16 -0800)
Makefile patch | blob | history
ships/Debug.ship patch | blob | history
ships/Dvi.ship patch | blob | history
ships/Video.ship patch | blob | history
src/edu/berkeley/fleet/fpga/Fpga.java patch | blob | history
src/edu/berkeley/fleet/fpga/main.ucf [deleted file] patch | blob | history

diff --git a/Makefile b/Makefile
index 8e07843..306b442 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -201,6 +201,7 @@ synth:
        echo '-g Persist:No' >> build/fpga/main.ut
 
        $(xilinx_ise)xst      -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
+       cat build/fpga/*.ucf > build/fpga/main.ucf
        $(xilinx_ise)ngdbuild -intstyle xflow -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
        $(xilinx_ise)map      -intstyle xflow -ol ${effort} -p $(device) -pr b -cm area -o main_map.ncd main.ngd main.pcf
        $(xilinx_ise)par      -intstyle xflow -ol ${effort} -w main_map.ncd main.ncd main.pcf
diff --git a/ships/Debug.ship b/ships/Debug.ship
index 0fbb9e0..88d4a15 100644 (file)
--- a/ships/Debug.ship
+++ b/ships/Debug.ship
@@ -138,6 +138,59 @@ public void service() {
     end
   end
 
+== UCF =================================================================
+
+Net clk_pin LOC=AH15;
+Net clk_pin  PERIOD = 10 ns HIGH 50%;  # 100Mhz
+
+# 33mhz clock
+#Net clk_pin LOC=AH17;
+#Net clk_pin TNM_NET = clk_pin;
+#TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%;  # 33Mhz
+
+Net rst_pin LOC=E9;
+Net rst_pin PULLUP;
+Net rst_pin TIG;
+
+#Net uart_cts LOC=G6;
+#Net uart_cts IOSTANDARD = LVCMOS33;
+#Net uart_cts TIG;
+
+#Net uart_rts LOC=F6;
+#Net uart_rts IOSTANDARD = LVCMOS33;
+#Net uart_rts TIG;
+
+Net uart_in LOC=AG15;
+#Net uart_in IOSTANDARD = LVCMOS33;
+Net uart_in TIG;
+Net uart_in PULLUP;
+
+Net uart_out LOC=AG20;
+#Net uart_out IOSTANDARD = LVCMOS33;
+Net uart_out TIG;
+Net uart_out PULLUP;
+
+NET  gpio_sw_c            LOC="AJ6";   # Bank 18, Vcco=3.3V, No DCI
+
+NET  gpio_led_c           LOC="E8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  gpio_led_e           LOC="AG23";  # Bank 2, Vcco=3.3V
+NET  gpio_led_n           LOC="AF13";  # Bank 2, Vcco=3.3V
+NET  gpio_led_s           LOC="AG12";  # Bank 2, Vcco=3.3V
+NET  gpio_led_w           LOC="AF23";  # Bank 2, Vcco=3.3V
+
+NET  gpio_led_0           LOC="H18";   # Bank 3, Vcco=2.5V, No DCI
+NET  gpio_led_1           LOC="L18";   # Bank 3, Vcco=2.5V, No DCI
+NET  gpio_led_2           LOC="G15";   # Bank 3, Vcco=2.5V, No DCI
+NET  gpio_led_3           LOC="AD26" | IOSTANDARD="LVCMOS18";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET  gpio_led_4           LOC="G16";   # Bank 3, Vcco=2.5V, No DCI
+NET  gpio_led_5           LOC="AD25" | IOSTANDARD="LVCMOS18";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET  gpio_led_6           LOC="AD24" | IOSTANDARD="LVCMOS18";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET  gpio_led_7           LOC="AE24" | IOSTANDARD="LVCMOS18";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+
+
+
+
+
 == Test ================================================================
 #expect 25
 
diff --git a/ships/Dvi.ship b/ships/Dvi.ship
index 335d9bd..d2259af 100644 (file)
--- a/ships/Dvi.ship
+++ b/ships/Dvi.ship
@@ -80,6 +80,8 @@ percolate up:    gpio_led_7   1
   wire dvi_xclk_p_unbuffered;
   wire dvi_xclk_n_unbuffered;
   wire dvi_xclk_fb;
+
+/*
   BUFG GBUF_FOR_DVI_CLOCK_N (.I(dvi_xclk_n_unbuffered), .O(dvi_xclk_n));
   BUFG GBUF_FOR_DVI_CLOCK_P (.I(dvi_xclk_p_unbuffered), .O(dvi_xclk_p));
   DCM  // 25Mhz VGA clock
@@ -94,6 +96,7 @@ percolate up:    gpio_led_7   1
       .CLKFX180 (dvi_xclk_n_unbuffered),
       .CLK0     (dvi_xclk_fb)
     );
+*/
 
   wire [31:0] vga_pixel_addr_;
   wire        vga_pixel_r;
@@ -158,7 +161,32 @@ percolate up:    gpio_led_7   1
     end
   end
 
-== Constants ========================================================
+== UCF ===============================================================
+NET  dvi_d0               LOC="AB8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d1               LOC="AC8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d2               LOC="AN12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d3               LOC="AP12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d4               LOC="AA9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d5               LOC="AA8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d6               LOC="AM13";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d7               LOC="AN13";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d8               LOC="AA10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d9               LOC="AB10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d10              LOC="AP14";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_d11              LOC="AN14";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_de               LOC="AE8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_h                LOC="AM12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_reset_b          LOC="AK6";   # Bank 18, Vcco=3.3V, No DCI
+NET  dvi_v                LOC="AM11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_xclk_n           LOC="AL10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET  dvi_xclk_p           LOC="AL11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+
+#NET  dvi_gpio1            LOC="N30" | IOSTANDARD="LVCMOS18";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
+#NET  dvi_iic_scl          LOC="U27" | IOSTANDARD="LVCMOS18";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
+#NET  dvi_iic_sda          LOC="T29" | IOSTANDARD="LVCMOS18";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
+
+
+== Constants =========================================================
 
 == Test ==============================================================
 #skip
diff --git a/ships/Video.ship b/ships/Video.ship
index b8ee01b..b614242 100644 (file)
--- a/ships/Video.ship
+++ b/ships/Video.ship
@@ -135,6 +135,59 @@ percolate up:         vga_clkout  1
     end
   end
 
+== UCF ===============================================================
+
+## VGA ##############################################################################
+
+#net "vga_hsync" loc   = f9;
+#net "vga_hsync" slew  = slow;
+#net "vga_hsync" drive = 2;
+#
+#net "vga_vsync" loc   = h10;
+#net "vga_vsync" slew  = slow;
+#net "vga_vsync" drive = 2;
+#
+#net "vga_clkout"  loc ="c12";
+#net "vga_clkout"  slew = fast;
+#net "vga_clkout"  drive = 8;
+#
+#net "vga_r<7>" loc ="h8";
+#net "vga_r<6>" loc ="c5";
+#net "vga_r<5>" loc ="h9";
+#net "vga_r<4>" loc ="g12";
+#net "vga_r<3>" loc ="g11";
+#net "vga_r<2>" loc ="g10";
+#net "vga_r<1>" loc ="f11";
+#net "vga_r<0>" loc ="f10";
+#net "vga_r<*>" slew = slow;
+#net "vga_r<*>" drive = 2;
+#
+#net "vga_g<7>" loc ="d5";
+#net "vga_g<6>" loc ="d4";
+#net "vga_g<5>" loc ="f8";
+#net "vga_g<4>" loc ="e13";
+#net "vga_g<3>" loc ="e12";
+#net "vga_g<2>" loc ="e11";
+#net "vga_g<1>" loc ="e9";
+#net "vga_g<0>" loc ="e8";
+#net "vga_g<*>" slew = slow;
+#net "vga_g<*>" drive = 2;
+#
+#net "vga_b<7>" loc ="c4";
+#net "vga_b<6>" loc ="c3";
+#net "vga_b<5>" loc ="d12";
+#net "vga_b<4>" loc ="d11";
+#net "vga_b<3>" loc ="d10";
+#net "vga_b<2>" loc ="d9";
+#net "vga_b<1>" loc ="c13";
+#net "vga_b<0>" loc ="g8";
+#net "vga_b<*>" slew = slow;
+#net "vga_b<*>" drive = 2;
+#
+#net "vga_*" iostandard = lvcmos33;
+#
+
+
 == Constants ========================================================
 
 == Test ==============================================================
diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java
index 0ca5447..d2b960c 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Fpga.java
+++ b/src/edu/berkeley/fleet/fpga/Fpga.java
@@ -13,7 +13,7 @@ import java.io.*;
 import edu.berkeley.fleet.two.*;
 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
-import static edu.berkeley.fleet.fpga.verilog.Verilog.PercolatedPort;
+import edu.berkeley.fleet.two.PercolatedPort;
 
 
 public class Fpga extends FleetTwoFleet {
@@ -165,6 +165,16 @@ public class Fpga extends FleetTwoFleet {
         try {
             if (sd.getSection("fpga")==null) return;
             String filename = sd.getName().toLowerCase();
+
+            if (sd.getSection("ucf") != null) {
+                File outf = new File("build/fpga/"+filename+".ucf");
+                FileOutputStream out = new FileOutputStream(outf);
+                PrintWriter pw = new PrintWriter(out);
+                pw.println(sd.getSection("ucf"));
+                pw.flush();
+                pw.close();
+            }
+
             File outf = new File("build/fpga/"+filename+".v");
             new File(outf.getParent()).mkdirs();
             System.err.println("writing to " + outf);
diff --git a/src/edu/berkeley/fleet/fpga/main.ucf b/src/edu/berkeley/fleet/fpga/main.ucf
deleted file mode 100644 (file)
index 799515f..0000000
--- a/src/edu/berkeley/fleet/fpga/main.ucf
+++ /dev/null
@@ -1,515 +0,0 @@
-## Clock, Reset ##############################################################################
-
-Net clk_pin LOC=AH17;
-
-Net rst_pin LOC=E9;
-Net rst_pin PULLUP;
-
-Net clk_pin TNM_NET = clk_pin;
-TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%;  # 33Mhz
-
-#Net clk_unbuffered TNM_NET = clk_unbuffered;
-#TIMESPEC TS_clk_unbuffered = PERIOD clk_unbuffered 20 ns;
-
-Net rst_pin TIG;
-
-## UART ##############################################################################
-
-#Net uart_cts LOC=G6;
-#Net uart_cts IOSTANDARD = LVCMOS33;
-#Net uart_cts TIG;
-
-#Net uart_rts LOC=F6;
-#Net uart_rts IOSTANDARD = LVCMOS33;
-#Net uart_rts TIG;
-
-Net uart_in LOC=AG15;
-#Net uart_in IOSTANDARD = LVCMOS33;
-Net uart_in TIG;
-Net uart_in PULLUP;
-
-Net uart_out LOC=AG20;
-#Net uart_out IOSTANDARD = LVCMOS33;
-Net uart_out TIG;
-Net uart_out PULLUP;
-
-## DVI ##############################################################################
-
-NET  dvi_d0               LOC="AB8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d1               LOC="AC8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d2               LOC="AN12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d3               LOC="AP12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d4               LOC="AA9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d5               LOC="AA8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d6               LOC="AM13";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d7               LOC="AN13";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d8               LOC="AA10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d9               LOC="AB10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d10              LOC="AP14";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_d11              LOC="AN14";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_de               LOC="AE8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_h                LOC="AM12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_reset_b          LOC="AK6";   # Bank 18, Vcco=3.3V, No DCI
-NET  dvi_v                LOC="AM11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_xclk_n           LOC="AL10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET  dvi_xclk_p           LOC="AL11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
-
-#NET  dvi_gpio1            LOC="N30" | IOSTANDARD="LVCMOS18";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
-#NET  dvi_iic_scl          LOC="U27" | IOSTANDARD="LVCMOS18";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
-#NET  dvi_iic_sda          LOC="T29" | IOSTANDARD="LVCMOS18";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
-
-NET  gpio_led_c           LOC="AJ6";   # Bank 18, Vcco=3.3V, No DCI
-NET  gpio_led_e           LOC="AK7";   # Bank 18, Vcco=3.3V, No DCI
-NET  gpio_led_n           LOC="U8";    # Bank 18, Vcco=3.3V, No DCI
-NET  gpio_led_s           LOC="V8";    # Bank 18, Vcco=3.3V, No DCI
-NET  gpio_led_w           LOC="AJ7";   # Bank 18, Vcco=3.3V, No DCI
-NET  gpio_led_0           LOC="H18";   # Bank 3, Vcco=2.5V, No DCI
-NET  gpio_led_1           LOC="L18";   # Bank 3, Vcco=2.5V, No DCI
-NET  gpio_led_2           LOC="G15";   # Bank 3, Vcco=2.5V, No DCI
-NET  gpio_led_3           LOC="AD26" | IOSTANDARD="LVCMOS18";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
-NET  gpio_led_4           LOC="G16";   # Bank 3, Vcco=2.5V, No DCI
-NET  gpio_led_5           LOC="AD25" | IOSTANDARD="LVCMOS18";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
-NET  gpio_led_6           LOC="AD24" | IOSTANDARD="LVCMOS18";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
-NET  gpio_led_7           LOC="AE24" | IOSTANDARD="LVCMOS18";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
-
-
-## VGA ##############################################################################
-
-#net "vga_hsync" loc   = f9;
-#net "vga_hsync" slew  = slow;
-#net "vga_hsync" drive = 2;
-#
-#net "vga_vsync" loc   = h10;
-#net "vga_vsync" slew  = slow;
-#net "vga_vsync" drive = 2;
-#
-#net "vga_clkout"  loc ="c12";
-#net "vga_clkout"  slew = fast;
-#net "vga_clkout"  drive = 8;
-#
-#net "vga_r<7>" loc ="h8";
-#net "vga_r<6>" loc ="c5";
-#net "vga_r<5>" loc ="h9";
-#net "vga_r<4>" loc ="g12";
-#net "vga_r<3>" loc ="g11";
-#net "vga_r<2>" loc ="g10";
-#net "vga_r<1>" loc ="f11";
-#net "vga_r<0>" loc ="f10";
-#net "vga_r<*>" slew = slow;
-#net "vga_r<*>" drive = 2;
-#
-#net "vga_g<7>" loc ="d5";
-#net "vga_g<6>" loc ="d4";
-#net "vga_g<5>" loc ="f8";
-#net "vga_g<4>" loc ="e13";
-#net "vga_g<3>" loc ="e12";
-#net "vga_g<2>" loc ="e11";
-#net "vga_g<1>" loc ="e9";
-#net "vga_g<0>" loc ="e8";
-#net "vga_g<*>" slew = slow;
-#net "vga_g<*>" drive = 2;
-#
-#net "vga_b<7>" loc ="c4";
-#net "vga_b<6>" loc ="c3";
-#net "vga_b<5>" loc ="d12";
-#net "vga_b<4>" loc ="d11";
-#net "vga_b<3>" loc ="d10";
-#net "vga_b<2>" loc ="d9";
-#net "vga_b<1>" loc ="c13";
-#net "vga_b<0>" loc ="g8";
-#net "vga_b<*>" slew = slow;
-#net "vga_b<*>" drive = 2;
-#
-#net "vga_*" iostandard = lvcmos33;
-#
-
-##############################################################################
-##############################################################################
-##############################################################################
-# DDR2
-
-############################################################################
-## 
-##  Xilinx, Inc. 2006            www.xilinx.com 
-##  ÐÇÆÚÒ» ¾ÅÔ 22 11:53:57 2008
-##  Generated by MIG Version 2.3
-##  
-############################################################################
-##  File name :       ddr2_sdram.ucf
-## 
-##  Details :     Constraints file
-##                    FPGA family:       virtex5
-##                    FPGA:              xc5vlx110t-ff1136
-##                    Speedgrade:        -1
-##                    Design Entry:      VERILOG
-##                    Frequency:         266.66 MHz
-##                    Design:            with Test bench
-##                    DCM Used:          Enable
-##                    Two Bytes per Bank:Disable
-##                    No.Of Controllers: 1
-##
-############################################################################ 
-
-############################################################################
-# Clock constraints                                                        #
-############################################################################
-
-NET "*/u_ddr2_infrastructure/sys_clk_ibufg" TNM_NET =  "SYS_CLK";
-TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5 ns HIGH 50 %;
-
-NET "*/u_ddr2_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
-TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;
-
-############################################################################
-########################################################################
-# Controller 0
-# Memory Device: DDR2_SDRAM->SODIMMs->MT4HTF3264HY-53E #
-# Data Width:     64 #
-# Data Mask:     1 #
-########################################################################
-
-################################################################################
-# I/O STANDARDS
-################################################################################
-
-NET  "ddr2_dq[*]"                               IOSTANDARD = SSTL18_II_DCI;
-NET  "ddr2_a[*]"                                IOSTANDARD = SSTL18_II;
-NET  "ddr2_ba[*]"                               IOSTANDARD = SSTL18_II;
-NET  "ddr2_ras_n"                               IOSTANDARD = SSTL18_II;
-NET  "ddr2_cas_n"                               IOSTANDARD = SSTL18_II;
-NET  "ddr2_we_n"                                IOSTANDARD = SSTL18_II;
-NET  "ddr2_cs_n[*]"                             IOSTANDARD = SSTL18_II;
-NET  "ddr2_odt[*]"                              IOSTANDARD = SSTL18_II;
-NET  "ddr2_cke[*]"                              IOSTANDARD = SSTL18_II;
-NET  "ddr2_dm[*]"                               IOSTANDARD = SSTL18_II;
-#NET  "sys_clk_p"                                IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
-#NET  "sys_clk_n"                                IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
-#NET  "clk200_p"                                 IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
-#NET  "clk200_n"                                 IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
-#NET  "sys_rst_n"                                IOSTANDARD = LVCMOS18;
-#NET  "phy_init_done"                           IOSTANDARD = LVCMOS18;
-#NET  "error"                                   IOSTANDARD = LVCMOS18;
-NET  "ddr2_dqs[*]"                              IOSTANDARD = DIFF_SSTL18_II_DCI;
-NET  "ddr2_dqs_n[*]"                            IOSTANDARD = DIFF_SSTL18_II_DCI;
-NET  "ddr2_ck[*]"                               IOSTANDARD = DIFF_SSTL18_II;
-NET  "ddr2_ck_n[*]"                             IOSTANDARD = DIFF_SSTL18_II;
-
-################################################################################
-# Location Constraints
-################################################################################
-
-NET  "ddr2_dq[0]"                                LOC = "AF30" ;              #Bank 17
-NET  "ddr2_dq[1]"                                LOC = "AK31" ;              #Bank 17
-NET  "ddr2_dq[2]"                                LOC = "AF31" ;              #Bank 17
-NET  "ddr2_dq[3]"                                LOC = "AD30" ;              #Bank 17
-NET  "ddr2_dq[4]"                                LOC = "AJ30" ;              #Bank 17
-NET  "ddr2_dq[5]"                                LOC = "AF29" ;              #Bank 17
-NET  "ddr2_dq[6]"                                LOC = "AD29" ;              #Bank 17
-NET  "ddr2_dq[7]"                                LOC = "AE29" ;              #Bank 17
-NET  "ddr2_dq[8]"                                LOC = "AH27" ;              #Bank 21
-NET  "ddr2_dq[9]"                                LOC = "AF28" ;              #Bank 21
-NET  "ddr2_dq[10]"                               LOC = "AH28" ;              #Bank 21
-NET  "ddr2_dq[11]"                               LOC = "AA28" ;              #Bank 21
-NET  "ddr2_dq[12]"                               LOC = "AG25" ;              #Bank 21
-NET  "ddr2_dq[13]"                               LOC = "AJ26" ;              #Bank 21
-NET  "ddr2_dq[14]"                               LOC = "AG28" ;              #Bank 21
-NET  "ddr2_dq[15]"                               LOC = "AB28" ;              #Bank 21
-NET  "ddr2_dq[16]"                               LOC = "AC28" ;              #Bank 21
-NET  "ddr2_dq[17]"                               LOC = "AB25" ;              #Bank 21
-NET  "ddr2_dq[18]"                               LOC = "AC27" ;              #Bank 21
-NET  "ddr2_dq[19]"                               LOC = "AA26" ;              #Bank 21
-NET  "ddr2_dq[20]"                               LOC = "AB26" ;              #Bank 21
-NET  "ddr2_dq[21]"                               LOC = "AA24" ;              #Bank 21
-NET  "ddr2_dq[22]"                               LOC = "AB27" ;              #Bank 21
-NET  "ddr2_dq[23]"                               LOC = "AA25" ;              #Bank 21
-NET  "ddr2_dq[24]"                               LOC = "AC29" ;              #Bank 17
-NET  "ddr2_dq[25]"                               LOC = "AB30" ;              #Bank 17
-NET  "ddr2_dq[26]"                               LOC = "W31" ;       #Bank 17
-NET  "ddr2_dq[27]"                               LOC = "V30" ;       #Bank 17
-NET  "ddr2_dq[28]"                               LOC = "AC30" ;              #Bank 17
-NET  "ddr2_dq[29]"                               LOC = "W29" ;       #Bank 17
-NET  "ddr2_dq[30]"                               LOC = "V27" ;       #Bank 17
-NET  "ddr2_dq[31]"                               LOC = "W27" ;       #Bank 17
-NET  "ddr2_dq[32]"                               LOC = "V29" ;       #Bank 17
-NET  "ddr2_dq[33]"                               LOC = "Y27" ;       #Bank 17
-NET  "ddr2_dq[34]"                               LOC = "Y26" ;       #Bank 17
-NET  "ddr2_dq[35]"                               LOC = "W24" ;       #Bank 17
-NET  "ddr2_dq[36]"                               LOC = "V28" ;       #Bank 17
-NET  "ddr2_dq[37]"                               LOC = "W25" ;       #Bank 17
-NET  "ddr2_dq[38]"                               LOC = "W26" ;       #Bank 17
-NET  "ddr2_dq[39]"                               LOC = "V24" ;       #Bank 17
-NET  "ddr2_dq[40]"                               LOC = "R24" ;       #Bank 19
-NET  "ddr2_dq[41]"                               LOC = "P25" ;       #Bank 19
-NET  "ddr2_dq[42]"                               LOC = "N24" ;       #Bank 19
-NET  "ddr2_dq[43]"                               LOC = "P26" ;       #Bank 19
-NET  "ddr2_dq[44]"                               LOC = "T24" ;       #Bank 19
-NET  "ddr2_dq[45]"                               LOC = "N25" ;       #Bank 19
-NET  "ddr2_dq[46]"                               LOC = "P27" ;       #Bank 19
-NET  "ddr2_dq[47]"                               LOC = "N28" ;       #Bank 19
-NET  "ddr2_dq[48]"                               LOC = "M28" ;       #Bank 19
-NET  "ddr2_dq[49]"                               LOC = "L28" ;       #Bank 19
-NET  "ddr2_dq[50]"                               LOC = "F25" ;       #Bank 19
-NET  "ddr2_dq[51]"                               LOC = "H25" ;       #Bank 19
-NET  "ddr2_dq[52]"                               LOC = "K27" ;       #Bank 19
-NET  "ddr2_dq[53]"                               LOC = "K28" ;       #Bank 19
-NET  "ddr2_dq[54]"                               LOC = "H24" ;       #Bank 19
-NET  "ddr2_dq[55]"                               LOC = "G26" ;       #Bank 19
-NET  "ddr2_dq[56]"                               LOC = "G25" ;       #Bank 19
-NET  "ddr2_dq[57]"                               LOC = "M26" ;       #Bank 19
-NET  "ddr2_dq[58]"                               LOC = "J24" ;       #Bank 19
-NET  "ddr2_dq[59]"                               LOC = "L26" ;       #Bank 19
-NET  "ddr2_dq[60]"                               LOC = "J27" ;       #Bank 19
-NET  "ddr2_dq[61]"                               LOC = "M25" ;       #Bank 19
-NET  "ddr2_dq[62]"                               LOC = "L25" ;       #Bank 19
-NET  "ddr2_dq[63]"                               LOC = "L24" ;       #Bank 19
-NET  "ddr2_a[12]"                                LOC = "T31" ;       #Bank 15      
-NET  "ddr2_a[11]"                                LOC = "R29" ;       #Bank 15      
-NET  "ddr2_a[10]"                                LOC = "J31" ;       #Bank 15      
-NET  "ddr2_a[9]"                                 LOC = "R28" ;       #Bank 15
-NET  "ddr2_a[8]"                                 LOC = "M31" ;       #Bank 15
-NET  "ddr2_a[7]"                                 LOC = "P30" ;       #Bank 15
-NET  "ddr2_a[6]"                                 LOC = "P31" ;       #Bank 15
-NET  "ddr2_a[5]"                                 LOC = "L31" ;       #Bank 15
-NET  "ddr2_a[4]"                                 LOC = "K31" ;       #Bank 15
-NET  "ddr2_a[3]"                                 LOC = "P29" ;       #Bank 15      
-NET  "ddr2_a[2]"                                 LOC = "N29" ;       #Bank 15      
-NET  "ddr2_a[1]"                                 LOC = "M30" ;       #Bank 15      
-NET  "ddr2_a[0]"                                 LOC = "L30" ;       #Bank 15      
-NET  "ddr2_ba[1]"                                LOC = "J30" ;       #Bank 15
-NET  "ddr2_ba[0]"                                LOC = "G31" ;       #Bank 15
-NET  "ddr2_ras_n"                                LOC = "H30" ;       #Bank 15
-NET  "ddr2_cas_n"                                LOC = "E31" ;       #Bank 15
-NET  "ddr2_we_n"                                 LOC = "K29" ;       #Bank 15
-NET  "ddr2_cs_n[0]"                              LOC = "L29" ;       #Bank 15
-NET  "ddr2_odt[0]"                               LOC = "F31" ;       #Bank 15
-NET  "ddr2_cke[0]"                               LOC = "T28" ;       #Bank 15
-NET  "ddr2_dm[0]"                                LOC = "AJ31" ;              #Bank 17
-NET  "ddr2_dm[1]"                                LOC = "AE28" ;              #Bank 21
-NET  "ddr2_dm[2]"                                LOC = "Y24" ;       #Bank 21
-NET  "ddr2_dm[3]"                                LOC = "Y31" ;       #Bank 17
-NET  "ddr2_dm[4]"                                LOC = "V25" ;       #Bank 17
-NET  "ddr2_dm[5]"                                LOC = "P24" ;       #Bank 19
-NET  "ddr2_dm[6]"                                LOC = "F26" ;       #Bank 19
-NET  "ddr2_dm[7]"                                LOC = "J25" ;       #Bank 19
-NET  "sys_clk_p"                                 LOC = "H14" ;       #Bank 3
-NET  "sys_clk_n"                                 LOC = "H15" ;       #Bank 3
-NET  "clk200_p"                                  LOC = "L19" ;       #Bank 3
-NET  "clk200_n"                                  LOC = "K19" ;       #Bank 3
-NET  "sys_rst_n"                                 LOC = "E9";           #Bank 20
-#NET  "phy_init_done"                             LOC = "H18" ;              #Bank 3
-NET  "error"                                     LOC = "F6";           #Bank 12
-NET  "ddr2_dqs[0]"                               LOC = "AA29" ;              #Bank 17
-NET  "ddr2_dqs_n[0]"                             LOC = "AA30" ;              #Bank 17
-NET  "ddr2_dqs[1]"                               LOC = "AK28" ;              #Bank 21
-NET  "ddr2_dqs_n[1]"                             LOC = "AK27" ;              #Bank 21
-NET  "ddr2_dqs[2]"                               LOC = "AK26" ;              #Bank 21
-NET  "ddr2_dqs_n[2]"                             LOC = "AJ27" ;              #Bank 21
-NET  "ddr2_dqs[3]"                               LOC = "AB31" ;              #Bank 17
-NET  "ddr2_dqs_n[3]"                             LOC = "AA31" ;              #Bank 17
-NET  "ddr2_dqs[4]"                               LOC = "Y28" ;       #Bank 17
-NET  "ddr2_dqs_n[4]"                             LOC = "Y29" ;       #Bank 17
-NET  "ddr2_dqs[5]"                               LOC = "E26" ;       #Bank 19
-NET  "ddr2_dqs_n[5]"                             LOC = "E27" ;       #Bank 19
-NET  "ddr2_dqs[6]"                               LOC = "H28" ;       #Bank 19
-NET  "ddr2_dqs_n[6]"                             LOC = "G28" ;       #Bank 19
-NET  "ddr2_dqs[7]"                               LOC = "G27" ;       #Bank 19
-NET  "ddr2_dqs_n[7]"                             LOC = "H27" ;       #Bank 19
-NET  "ddr2_ck[0]"                                LOC = "AK29" ;              #Bank 21
-NET  "ddr2_ck_n[0]"                              LOC = "AJ29" ;              #Bank 21
-NET  "ddr2_ck[1]"                                LOC = "E28" ;       #Bank 19
-NET  "ddr2_ck_n[1]"                              LOC = "F28" ;       #Bank 19
-
-################################################################################
-#IDELAYCTRL Location Constraints
-################################################################################
-
-INST "*/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;
-INST "*/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y2;
-INST "*/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X0Y6;
-
-###############################################################################
-# Define multicycle paths - these paths may take longer because additional
-# time allowed for logic to settle in calibration/initialization FSM
-###############################################################################
-
-# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
-#          multicycle paths from originating flip-flop to ANY destination
-#          flip-flop (or in some cases, it can also be a BRAM)
-# MUX Select for either rising/falling CLK0 for 2nd stage read capture
-INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
-TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
-"TS_SYS_CLK" * 4;
-# MUX select for read data - optional delay on data to account for byte skews
-#INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
-#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
-#"TS_SYS_CLK" * 4;
-# Calibration/Initialization complete status flag (for PHY logic only) - can
-# be used to drive both flip-flops and BRAMs
-INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
-TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
-"TS_SYS_CLK" * 4;
-TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
-"TS_SYS_CLK" * 4;
-# Select (address) bits for SRL32 shift registers used in stage3/stage4
-# calibration
-INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
-TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;
-INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
-TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;
-INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
-  TNM = "TNM_CAL_RDEN_DLY";
-TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
-  "TS_SYS_CLK" * 4;
-
-###############################################################################
-# DQS Read Post amble Glitch Squelch circuit related constraints
-###############################################################################
-
-###############################################################################
-# LOC placement of DQS-squelch related IDDR and IDELAY elements
-# Each circuit can be located at any of the following locations:
-#  1. Unused "N"-side of DQS differential pair I/O
-#  2. DM data mask (output only, input side is free for use)
-#  3. Any output-only site
-###############################################################################
-
-INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y96";
-INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y96";
-INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y58";
-INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y58";
-INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y62";
-INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y62";
-INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y100";
-INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y100";
-INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y102";
-INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y102";
-INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y256";
-INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y256";
-INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y260";
-INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y260";
-INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y262";
-INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y262";
-
-###############################################################################
-# LOC and timing constraints for flop driving DQS CE enable signal
-# from fabric logic. Even though the absolute delay on this path is
-# calibrated out (when synchronizing this output to DQS), the delay
-# should still be kept as low as possible to reduce post-calibration
-# voltage/temp variations - these are roughly proportional to the
-# absolute delay of the path
-###############################################################################
-
-INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff"  LOC = SLICE_X0Y48;
-INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff"  LOC = SLICE_X0Y29;
-INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff"  LOC = SLICE_X0Y31;
-INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff"  LOC = SLICE_X0Y50;
-INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff"  LOC = SLICE_X0Y51;
-INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff"  LOC = SLICE_X0Y128;
-INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff"  LOC = SLICE_X0Y130;
-INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff"  LOC = SLICE_X0Y131;
-
-# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
-# two parts to this path: (1) from fabric flop to IDELAY, (2) from
-# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
-# This can be relaxed by the user for lower frequencies:
-# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
-# In general PAR should be able to route this
-# within 900ps over all speed grades.
-NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
-NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
-
-###############################################################################
-# "Half-cycle" path constraint from IDDR to CE pin for all DQ IDDR's
-# for DQS Read Post amble Glitch Squelch circuit
-###############################################################################
-
-# Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
-#  where slack account for rise-time of DQS on board. For now assume slack = 
-#  0.400ns (based on initial SPICE simulations, assumes use of ODT), so 
-#  time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
-INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
-INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
-TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;
-
-###############################################################################
-# MIG 2.2: Prevent unrelated logic from being packed into any slices used
-#          by read data capture RPM's - if unrelated logic gets packed into
-#          these slices, it could cause the DIRT strings that define the
-#          IDDR -> fabric flop routing to become unroutable during PAR stage
-#          (unrelated logic may require routing resources required by the
-#          DIRT strings - MAP does not currently take into account DIRT
-#          strings when placing logic
-###############################################################################
-
-AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
-
-###############################################################################
-# Location constraints for DQ read-data capture flops in fabric (for 2nd
-# stage capture)
-###############################################################################
-
-INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y42;            #  AF30      X0Y22    *
-INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y43;            #  AK31      X0Y23    
-INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y45;            #  AF31      X0Y25    
-INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y46;            #  AD30      X0Y26    
-INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y41;            #  AJ30      X0Y21    
-INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y42;            #  AF29      X0Y22    ***
-INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y44;            #  AD29      X0Y24    
-INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y44;            #  AE29      X0Y24    
-INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y28;            #  AH27      X0Y8     ***
-INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y32;            #  AF28      X0Y12    
-INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y33;           #  AH28      X0Y13    
-INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y34;           #  AA28      X0Y14    
-INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y26;           #  AG25      X0Y6     
-INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y28;           #  AJ26      X0Y8     *
-INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y33;           #  AG28      X0Y13    
-INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y34;           #  AB28      X0Y14    
-INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y35;           #  AC28      X0Y15    
-INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y36;           #  AB25      X0Y16    ***
-INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y38;           #  AC27      X0Y18    
-INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y39;           #  AA26      X0Y19    
-INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y36;           #  AB26      X0Y16    *
-INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y37;           #  AA24      X0Y17    
-INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y38;           #  AB27      X0Y18    
-INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y39;           #  AA25      X0Y19    
-INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y46;           #  AC29      X0Y26    
-INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y49;           #  AB30      X0Y29    ***
-INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y53;           #  W31       X0Y33    
-INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y55;           #  V30       X0Y35    
-INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y49;           #  AC30      X0Y29    *
-INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y52;           #  W29       X0Y32    
-INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y54;           #  V27       X0Y34    ***
-INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y56;           #  W27       X0Y36    
-INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y52;           #  V29       X0Y32    
-INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y56;           #  Y27       X0Y36    
-INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y58;           #  Y26       X0Y38    
-INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y59;           #  W24       X0Y39    
-INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y54;           #  V28       X0Y34   * 
-INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y57;           #  W25       X0Y37    
-INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y58;           #  W26       X0Y38    
-INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y59;           #  V24       X0Y39    
-INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y120;          #  R24       X0Y100   
-INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y121;          #  P25       X0Y101   
-INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y122;          #  N24       X0Y102   
-INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y123;          #  P26       X0Y103   
-INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y120;          #  T24       X0Y100   
-INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y121;          #  N25       X0Y101   
-INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y123;          #  P27       X0Y103   
-INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y124;          #  N28       X0Y104   
-INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y124;          #  M28       X0Y104   
-INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y126;          #  L28       X0Y106   
-INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y132;          #  F25       X0Y112   
-INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y133;          #  H25       X0Y113   
-INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y125;          #  K27       X0Y105   
-INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y126;          #  K28       X0Y106   
-INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y133;          #  H24       X0Y113   
-INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y134;          #  G26       X0Y114   
-INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y134;          #  G25       X0Y114   
-INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y136;          #  M26       X0Y116   
-INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y137;          #  J24       X0Y117   
-INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y138;          #  L26       X0Y118   
-INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y135;          #  J27       X0Y115   
-INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y136;          #  M25       X0Y116   
-INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y138;          #  L25       X0Y118   
-INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y139;          #  L24       X0Y119   
-
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