// host -> fpga
data_to_fleet_read_enable <= 0;
if (!data_to_fleet_empty && `out_empty && !data_to_fleet_read_enable) begin
- out_d <= { out_d[41:0], data_to_fleet[7:0] };
+ out_d <= { out_d[43:0], data_to_fleet[5:0] };
data_to_fleet_read_enable <= 1;
- if (count_in==7) begin
+ if (count_in==9) begin
count_in <= 0;
`fill_out
end else begin
out = fpga.PACKET_SIGNAL.setval(out, 0);
out = fpga.PACKET_DEST.setval(out, ((FpgaPath)dispatchFrom.getPath(d, null)).toLong());
synchronized(this) {
- for(int i=7; i>=0; i--)
- dos.write(BitManipulations.getIntField(i*8+7, i*8, out));
+ for(int i=9; i>=0; i--)
+ dos.write(BitManipulations.getIntField(i*6+7, i*6, out));
}
} catch (Exception e) {
throw new RuntimeException(e);